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[PATCH 3/4] mwifiex: support for event done interrupt

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This patch adds support for writing CPU event interrupt done back
to device.
Patch also increases interrupt buffer ring size from 4 to 8.

Signed-off-by: Avinash Patil <patila@xxxxxxxxxxx>
Signed-off-by: Cathy Luo <cluo@xxxxxxxxxxx>                                                                                                                                                                                                                                   
---
 drivers/net/wireless/mwifiex/pcie.c | 7 +++++++
 drivers/net/wireless/mwifiex/pcie.h | 5 +++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/mwifiex/pcie.c b/drivers/net/wireless/mwifiex/pcie.c
index fbb0550..1f6e687 100644
--- a/drivers/net/wireless/mwifiex/pcie.c
+++ b/drivers/net/wireless/mwifiex/pcie.c
@@ -1726,6 +1726,13 @@ static int mwifiex_pcie_process_event_ready(struct mwifiex_adapter *adapter)
                   buffer is released. This is just to make things simpler,
                   we need to find a better method of managing these buffers.
                */
+       } else {
+               if (mwifiex_write_reg(adapter, PCIE_CPU_INT_EVENT,
+                                     CPU_INTR_EVENT_DONE)) {
+                       dev_warn(adapter->dev,
+                                "Write register failed\n");
+                       return -1;
+               }
        }

        return 0;
diff --git a/drivers/net/wireless/mwifiex/pcie.h b/drivers/net/wireless/mwifiex/pcie.h
index a1a8fd3..200e8b0 100644
--- a/drivers/net/wireless/mwifiex/pcie.h
+++ b/drivers/net/wireless/mwifiex/pcie.h
@@ -40,8 +40,8 @@
 #define MWIFIEX_TXBD_MASK                      0x3F
 #define MWIFIEX_RXBD_MASK                      0x3F

-#define MWIFIEX_MAX_EVT_BD                     0x04
-#define MWIFIEX_EVTBD_MASK                     0x07
+#define MWIFIEX_MAX_EVT_BD                     0x08
+#define MWIFIEX_EVTBD_MASK                     0x0f

 /* PCIE INTERNAL REGISTERS */
 #define PCIE_SCRATCH_0_REG                             0xC10
@@ -69,6 +69,7 @@
 #define CPU_INTR_DOOR_BELL                             BIT(1)
 #define CPU_INTR_SLEEP_CFM_DONE                        BIT(2)
 #define CPU_INTR_RESET                                 BIT(3)
+#define CPU_INTR_EVENT_DONE                            BIT(5)

 #define HOST_INTR_DNLD_DONE                            BIT(0)
 #define HOST_INTR_UPLD_RDY                             BIT(1)
-- 
1.8.1.4
--
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