On 16 October 2013 06:46, Kalle Valo <kvalo@xxxxxxxxxxxxxxxx> wrote:
> From: Michal Kazior <michal.kazior@xxxxxxxxx>
>
> Hardware revision 2 does not support cold reset
> correctly. As such it would sometimes lead to host
> machine freeze or data bus errors.
>
> The patch introduces warm reset function which is
> used instead of the cold reset one. It also moves
> the reset before interrupts are being set up to
> prevent any kind of spurious interrupts from being
> handled.
>
> kvalo: use ath10k_pci_write32() style wrappers, fix long
> lines
>
> Signed-off-by: Michal Kazior <michal.kazior@xxxxxxxxx>
> Signed-off-by: Kalle Valo <kvalo@xxxxxxxxxxxxxxxx>
> ---
[...]
> @@ -1825,16 +1824,78 @@ static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
> ath10k_pci_sleep(ar);
> }
>
> -static int ath10k_pci_hif_power_up(struct ath10k *ar)
> +static int ath10k_pci_warm_reset(struct ath10k *ar)
> {
> struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
> int ret;
> + u32 val;
>
> - ret = ath10k_pci_start_intr(ar);
> - if (ret) {
> - ath10k_err("could not start interrupt handling (%d)\n", ret);
> - goto err;
> - }
> + ath10k_dbg(ATH10K_DBG_BOOT, "performing warm chip reset\n");
> +
> + ret = ath10k_do_pci_wake(ar);
> + if (ret)
> + return ret;
> +
> + ath10k_dbg(ATH10K_DBG_BOOT,
> + "pci intr cause 0x%08x cpu intr 0x%08x (before)\n",
> + ath10k_pci_core_read32(ar, PCIE_INTR_CAUSE_ADDRESS),
> + ath10k_pci_core_read32(ar, CPU_INTR_ADDRESS));
> +
> + /* disable pending irqs */
> + ath10k_pci_core_write32(ar, PCIE_INTR_ENABLE_ADDRESS, 0);
> + ath10k_pci_core_write32(ar, PCIE_INTR_CLR_ADDRESS, ~0);
These use SOC_CORE_BASE_ADDRESS as the suffix, not the RTC_SOC_BASE_ADDRESS.
> + ath10k_dbg(ATH10K_DBG_BOOT,
> + "pci intr cause 0x%08x cpu intr 0x%08x (after)\n",
> + ath10k_pci_core_read32(ar, PCIE_INTR_CAUSE_ADDRESS),
> + ath10k_pci_core_read32(ar, CPU_INTR_ADDRESS));
Ditto. These are in SOC_CORE_BASE_ADDRESS group.
Michał
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