On Tue, 2013-05-07 at 11:30 +0300, Luciano Coelho wrote: > From: Ido Reis <idor@xxxxxx> > > In PG2.0 there is an issue where PHY's FDSP Code RAM sometimes gets > corrupted when exiting from ELP mode. This issue is related to FDSP > Code RAM clock implementation. > > PG2.1 introduces a HW fix for this issue that requires the driver to > change the FDSP Code Ram clock settings (mux it to ATGP clock instead > of its own clock). > > This workaround uses PHY_FPGA_SPARE_1 register and is relevant to WL8 > PG2.1 devices. > > The fix is also backward compatible with older PG2.0 devices where the > register PHY_FPGA_SPARE_1 is not used and not connected. > > The fix is done in the wl18xx_pre_upload function (must be performed > before uploading the FW code) and includes the following steps: > > 1. Disable FDSP clock > 2. Set ATPG clock toward FDSP Code RAM rather than its own clock. > 3. Re-enable FDSP clock > > Signed-off-by: Yair Shapira <yair.shapira@xxxxxx> > Signed-off-by: Ido Reis <idor@xxxxxx> > Signed-off-by: Arik Nemtsov <arik@xxxxxxxxxx> > Signed-off-by: Luciano Coelho <coelho@xxxxxx> > --- > > This replaces a patch that was part of a series that Arik sent a while > ago. Just did some clean-ups and tested with PG2.1. Applied and pushed. -- Luca. -- To unsubscribe from this list: send the line "unsubscribe linux-wireless" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
