On 5/10/21 1:25 AM, Shaokun Zhang wrote:
Hi Guenter,
On 2021/5/10 12:25, Guenter Roeck wrote:
On 5/9/21 8:41 PM, Shaokun Zhang wrote:
Arm Base System Architecture 1.0[1] has introduced watchdog
revision 1 that increases the length the watchdog offset
Is that how they call the watchdog count register ?
I think yes.
Also, doesn't that mean that the maximum timeout supported
by the hardware is now larger ?
No, maximum timeout is the same. But the clock can be higher than
before. For Armv8.6, The frequency of CNTFRQ_EL0 is standardized to
a frequency of 1GHz which will set gwdt->clk. If the timeout is
greater than 4(second), the 32-bit counter(WOR) is not enough.
The maximuma timeout is limited with
wdd->max_hw_heartbeat_ms = U32_MAX / gwdt->clk * 1000;
You did not update that calculation. That means that the maximuma
timeout is still U32_MAX / gwdt->clk * 1000, which still fits
into 32 bit.
Please correct me if I am missing something.
Guenter
