On 05/26/2016 12:06 PM, Carlo Caione wrote:
> On 26/05/16 09:51, Neil Armstrong wrote:
>> Add watchdog specific driver for Amlogic Meson GXBB SoC.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@xxxxxxxxxxxx>
>> +
>
> [...]
>> +#define DEFAULT_TIMEOUT 10 /* seconds */
>> +
>> +#define GXBB_WDT_CTRL_REG 0x0
>> +#define GXBB_WDT_CTRL1_REG 0x4
>> +#define GXBB_WDT_TCNT_REG 0x8
>> +#define GXBB_WDT_RSET_REG 0xc
>> +
>> +#define GXBB_WDT_CTRL_EE_RESET_NOW BIT(26)
>> +
>> +#define GXBB_WDT_CTRL_CLKDIV_EN BIT(25)
>> +#define GXBB_WDT_CTRL_CLK_EN BIT(24)
>> +#define GXBB_WDT_CTRL_IRQ_EN BIT(23)
>> +#define GXBB_WDT_CTRL_EE_RESET BIT(21)
>> +#define GXBB_WDT_CTRL_XTAL_SEL (0)
>> +#define GXBB_WDT_CTRL_CLK81_SEL BIT(19)
>> +#define GXBB_WDT_CTRL_EN BIT(18)
>> +#define GXBB_WDT_CTRL_DIV_MASK (BIT(18)-1)
>> +
>> +#define GXBB_WDT_CTRL1_GPIO_PULSE BIT(17)
>> +#define GXBB_WDT_CTRL1_GPIO_POL_RESET_0 BIT(16)
>> +#define GXBB_WDT_CTRL1_GPIO_POL_RESET_1 (0)
>> +#define GXBB_WDT_CTRL1_GPIO_PULSE_CNT (BIT(16)-1)
>> +
>> +#define GXBB_WDT_TCNT_SETUP_MASK (BIT(16)-1)
>> +#define GXBB_WDT_TCNT_CNT_SHIFT 16
>
> Indentation
>
> [...]
>> +int meson_gxbb_wdt_set_timeout(struct watchdog_device *wdt_dev,
>> + unsigned int timeout)
>> +{
>> + struct meson_gxbb_wdt *data = watchdog_get_drvdata(wdt_dev);
>> +
>> + if (watchdog_active(wdt_dev))
>> + meson_gxbb_wdt_stop(wdt_dev);
>> +
>> + meson_gxbb_wdt_ping(wdt_dev);
>> +
>> + writel(timeout*1000, data->reg_base + GXBB_WDT_TCNT_REG);
>
> nit: spaces around "*"
>
> [...]
>> + data->clk = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(data->clk))
>> + return PTR_ERR(data->clk);
>> +
>> + clk_prepare_enable(data->clk);
>
> Do we need to merge the clock controller driver before this?
It's not necessary, currently it only selects the xtal source, so it's works with the current upstream architecture.
Neil
>
> Cheers,
>
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