Hi Tom, On Thu, 2013-05-02 at 04:40 +0100, Tom Lyon wrote: > Virtiio_mmio attempts to mimic the layout of some control registers from > virtio_pci. These registers, in particular VIRTIO_MMIO_QUEUE_SEL and > VIRTIO_PCI_QUEUE_SEL, > are active in nature, and not just passive like a normal memory > location. Thus, the host side must react immediately upon write of > these registers to map some other registers (queue address, size, etc) > to queue-specific locations. This is just not possible for mmio, and, I > would argue, not desirable for PCI either. Could you, please, elaborate more about the environment you are talking about here? The intention of the MMIO device is to behave like a normal memory mapped peripheral, say serial port. In the world of architecture without separate I/O address space (like ARM, MIPS, SH-4 to name only those I know anything about), such peripherals are usually mapped into the virtual address space with special attributes, eg. guaranteeing transactions order. That's why the host can "react immediately" and to my knowledge multi-queue virtio devices work just fine. I'd love see comments from someone with x86 expertise in such areas. Maybe we are missing some memory barriers here? So the host implementation would have a chance to react to the QUEUE_SEL access before servicing other transactions? Regards Paweł _______________________________________________ Virtualization mailing list Virtualization@xxxxxxxxxxxxxxxxxxxxxxxxxx https://lists.linuxfoundation.org/mailman/listinfo/virtualization
