On 04/10/2013 09:31 AM, Eric Northup wrote: >> >> If the effect is measurable I agree it is a legitimate optimization. At >> one point there was a suggestion to make the code in the IDT vectors >> differ based on the which interrupt was registed. While that can also >> reduce cache misses that can get hairy very quickly, and of course that >> would require read-write IDTs. > > read-write IDT or GDT are fine: map them twice, once read+write, once > read-only. Point the GDTR and IDTR at the read-only alias. > Well, it is weaker, because if you can discover the pointer to the writable alias you win. Now, as has been pointed out the GDT needs to be writable on 32 bits as a matter of hardware requirement. However, doing it for 64 bits only is probably enough of a win. -hpa _______________________________________________ Virtualization mailing list Virtualization@xxxxxxxxxxxxxxxxxxxxxxxxxx https://lists.linuxfoundation.org/mailman/listinfo/virtualization
