On Tue, Nov 19, 2013 at 03:12:36AM +0800, Paul Zimmerman wrote: > > From: Pratyush Anand [mailto:pratyush.anand@xxxxxx] > > Sent: Sunday, November 17, 2013 8:24 PM > > > > Hi Paul/Felipe, > > > > Any comment? > > > > Regards > > Pratyush > > > > On Fri, Nov 15, 2013 at 09:34:44AM +0530, Pratyush Anand wrote: > > > Hi, > > > > > > Patch "usb: dwc3: gadget: drop dwc3 manual phy control" says > > > > > > "Recent versions of the core, can suspend and resume the PHYs > > > automatically, so we don't need to fiddle with dwc3's Global PHY > > > registers at all." > > > > > > First part of the statement is true, but only when bit 17 of > > > GUSB3PIPECTL and bit 6 of GUSB2PHYCFG is set, no? > > > > > > Recommended reset value of this bit in DRD/OTG mode is '0' and in > > > other mode is '1'. Specs recommends to set this value after core > > > initialization is complete. > > > > > > So, shouldn't software always set these bits after core > > > initialization to take care of the controller where this bit was > > > not set at reset. > > Yes, it probably should, although it only matters for DRD/OTG mode, if > the core was configured with the recommended reset values for those bits. > > Note that the core should still work fine the way things are now, it's > just that a little power will be wasted because one of the phys is not > suspended when it could be. > > On a related subject, since version 2.10a the databook has recommended > that bit 6 of GUSB2PHYCFG be cleared before issuing any of the DEPCMD > commands, and then set again after the command has completed. This is to > avoid a potential lockup of the core. I don't believe the DWC3 driver > has implemented this yet. > Thanks a lot Paul for the clarification. Regards Pratyush > -- > Paul -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
