> From: Matthijs Kooijman [mailto:matthijs@xxxxxxxx] > Sent: Tuesday, July 16, 2013 7:51 AM > > Hi Paul, > > could you perhaps look up some documentation on the PCGCTL register for me? > > The issue John and I have been facing is that on one particular board, > the dwc2 driver fails to initialize saying: > > dwc2 101c0000.usb: Bad value for GSNPSID: 0x00000000 > > We've traced this back to the initalization done in the uboot bootloader. On > the broken board, uboot does (among other things): > > RT2882_REG(0xB01C0E00) = 0xF; //disable USB module, optimize for power-saving > > E.g, enable bits 0-3 in the PCGCTL register. I can reproduce this > problem on the "good" boards by doing the same thing somewhere early in > the kernel initalization. Further experimentation shows that writing 0x4 > to the PCGTL register is enough to break things. > > In order to better understand what's going on, I'm not wondering what > the meaning of the PCGCTL register is, and in particular bit 2 (0x4). > Could you clarify? Hi Matthijs, Here is the description of bits 3:0 from the databook: 3 Reset Power-Down Modules (RstPdwnModule) This bit is valid only in Partial Power-Down mode. The application sets this bit when the power is turned off. The application clears this bit after the power is turned on and the PHY clock is up. Note: The read/write of all core registers are possible only when this bit is set to 1'b0. Reset: 1'b0 2 Power Clamp (PwrClmp) This bit is valid only in Partial Power-Down mode (OTG_EN_PWROPT = 1). The application sets this bit before the power is turned off to clamp the signals between the power-on modules and the power-off modules. The application clears the bit to disable the clamping before the power is turned on. Reset: 1'b0 1 Gate Hclk (GateHclk) The application sets this bit to gate hclk to modules other than the AHB Slave and Master and wakeup logic when the USB is suspended or the session is not valid. The application clears this bit when the USB is resumed or a new session starts. This register is present only when OTG_EN_PWROPT = 1. Reset: 1'b0 0 Stop Pclk (StopPclk) The application sets this bit to stop the PHY clock (phy_clk) when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts. Reset: 1'b0 So it sounds like setting these bits to 0xf in the bootloader is a bad idea. Or at least, the first thing the driver should do is set them all to 0. > As said, on most of our boards this problem does not occur. Reviewing > a the bootloader assembler code shows that those boards do not write the > PCGCTL register. However, the reference uboot code from Ralink _does_ > write the register, so it seems good to make the driver work even when > this particular bit was enabled. > > Simply resetting the PCGCTL register in hcd_init or somewhere around > there fixes the problem. However, John suggested an even more generic > problem: using the kernel-wide reset controller driver to completely > reset the dwc controller before initializing it (by calling > device_reset()). On the RT3052 SoC there is a global reset register > which can be used to reset the dwc controller. Support for this register > is being added by John currently. Does this seem sane? There should be nothing wrong with resetting the controller before initializing it, so if that works for you I would say go for it. -- Paul -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
