Hi Paul, could you perhaps look up some documentation on the PCGCTL register for me? The issue John and I have been facing is that on one particular board, the dwc2 driver fails to initialize saying: dwc2 101c0000.usb: Bad value for GSNPSID: 0x00000000 We've traced this back to the initalization done in the uboot bootloader. On the broken board, uboot does (among other things): RT2882_REG(0xB01C0E00) = 0xF; //disable USB module, optimize for power-saving E.g, enable bits 0-3 in the PCGCTL register. I can reproduce this problem on the "good" boards by doing the same thing somewhere early in the kernel initalization. Further experimentation shows that writing 0x4 to the PCGTL register is enough to break things. In order to better understand what's going on, I'm not wondering what the meaning of the PCGCTL register is, and in particular bit 2 (0x4). Could you clarify? As said, on most of our boards this problem does not occur. Reviewing a the bootloader assembler code shows that those boards do not write the PCGCTL register. However, the reference uboot code from Ralink _does_ write the register, so it seems good to make the driver work even when this particular bit was enabled. Simply resetting the PCGCTL register in hcd_init or somewhere around there fixes the problem. However, John suggested an even more generic problem: using the kernel-wide reset controller driver to completely reset the dwc controller before initializing it (by calling device_reset()). On the RT3052 SoC there is a global reset register which can be used to reset the dwc controller. Support for this register is being added by John currently. Does this seem sane? Gr. Matthijs -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
