Re: [PATCH] jacinto6 : usb3_phy: Updated dpll M,N values.

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On Fri, Jun 21, 2013 at 10:46:10AM -0500, Ruchika Kharwar wrote:
> Addition of the M and N recommended values for the USB3 PHY DPLL.
> Sysclk for DRA7xx is 20MHz.
> This yields:
> Clk = 20MHz * M/(N+1) = 20MHz * 1000 /(7+1) = 2.5 Ghz
> 
> Signed-off-by: Nikhil Devshatwar <nikhil.nd@xxxxxx>
> Signed-off-by: Ruchika Kharwar <ruchika@xxxxxx>

this won't apply since you had already sent me another version. Please
send in a fix up patch if that's wrong.

-- 
balbi

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