Derived from isp1760-hcd driver.
isp1763 is different in this way compred to isp1760:
- 16 Proprietary Transfer Descriptor (instead of 32)
- 20 KB payload space (instead of 60KB)
- 16/8 bit parallel bus access (instead of 32/16)
- Not all register are 32-bit
- Timing delay (100 ns) between SKIPMAP writes
TODO:
A bunch of functions can be unified between isp1760-hcd and this driver.
NOTE:
Found to be working on some mass storage device, but failing enumeration
on others on my platform. More testing and tuning per platform maybe
needed.
Signed-off-by: Richard Retanubun <richardretanubun@xxxxxxxxxxxxx>
---
drivers/usb/host/Kconfig | 15 +
drivers/usb/host/Makefile | 2 +
drivers/usb/host/isp1763-hcd.c | 2366 ++++++++++++++++++++++++++++++++++++++++
drivers/usb/host/isp1763-hcd.h | 257 +++++
drivers/usb/host/isp1763-if.c | 523 +++++++++
include/linux/usb/isp1763.h | 37 +
6 files changed, 3200 insertions(+)
create mode 100644 drivers/usb/host/isp1763-hcd.c
create mode 100644 drivers/usb/host/isp1763-hcd.h
create mode 100644 drivers/usb/host/isp1763-if.c
create mode 100644 include/linux/usb/isp1763.h
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index c59a112..d1dc278 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -284,6 +284,21 @@ config USB_ISP1760_HCD
To compile this driver as a module, choose M here: the
module will be called isp1760.
+config USB_ISP1763_HCD
+ tristate "ISP 1763 HCD support"
+ depends on USB
+ ---help---
+ The ISP1763 chip is a USB 2.0 host controller.
+
+ This driver does not support isochronous transfers or OTG.
+ This USB controller is usually attached to a non-DMA-Master
+ capable bus. NXP's eval kit brings this chip on PCI card
+ where the chip itself is behind a PLB to simulate such
+ a bus.
+
+ To compile this driver as a module, choose M here: the
+ module will be called isp1763.
+
config USB_ISP1362_HCD
tristate "ISP1362 HCD support"
depends on USB
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 001fbff..f7dc536 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -5,6 +5,7 @@
ccflags-$(CONFIG_USB_DEBUG) := -DDEBUG
isp1760-y := isp1760-hcd.o isp1760-if.o
+isp1763-y := isp1763-hcd.o isp1763-if.o
fhci-y := fhci-hcd.o fhci-hub.o fhci-q.o
fhci-y += fhci-mem.o fhci-tds.o fhci-sched.o
@@ -40,6 +41,7 @@ obj-$(CONFIG_USB_SL811_CS) += sl811_cs.o
obj-$(CONFIG_USB_U132_HCD) += u132-hcd.o
obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o
+obj-$(CONFIG_USB_ISP1763_HCD) += isp1763.o
obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o
obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o
obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o
diff --git a/drivers/usb/host/isp1763-hcd.c b/drivers/usb/host/isp1763-hcd.c
new file mode 100644
index 0000000..7dd70f9
--- /dev/null
+++ b/drivers/usb/host/isp1763-hcd.c
@@ -0,0 +1,2366 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published
+ * by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ *
+ * Description:
+ *
+ * isp1763 Host Controller Driver
+ *
+ * Based on isp1760 driver by:
+ * Sebastian Andrzej Siewior <sebastian@xxxxxxxxxxxxx>
+ * Arvid Brodin <arvid.brodin@xxxxxxxx>
+ * and pehci hcd from ST-Ericsson wired support <wired.support@xxxxxxxxxxxxxx>
+ *
+ */
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/usb.h>
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/timer.h>
+#include <asm/unaligned.h>
+#include <asm/cacheflush.h>
+#include <linux/gpio.h>
+#include <linux/usb/hcd.h>
+#include <linux/usb/isp1763.h>
+
+#include "isp1763-hcd.h"
+
+#define NUM_OF_PTD 16 /* isp1760 have 32 max PTDs; isp 1763 have 16 */
+
+static struct kmem_cache *qtd_cachep;
+static struct kmem_cache *qh_cachep;
+static struct kmem_cache *urb_listitem_cachep;
+
+enum queue_head_types {
+ QH_CONTROL,
+ QH_BULK,
+ QH_INTERRUPT,
+ QH_END
+};
+
+struct isp1763_hcd {
+ u32 hcs_params;
+ spinlock_t lock;
+ struct slotinfo atl_slots[NUM_OF_PTD];
+ u16 atl_done_map;
+ struct slotinfo int_slots[NUM_OF_PTD];
+ u16 int_done_map;
+ struct memory_chunk memory_pool[BLOCKS];
+ struct list_head qh_list[QH_END];
+
+ /* periodic schedule support */
+#define DEFAULT_I_TDPS 1024
+ unsigned periodic_size;
+ unsigned i_thresh;
+ unsigned long reset_done;
+ unsigned long next_statechange;
+ unsigned int devflags;
+
+ int rst_gpio;
+};
+
+static inline struct isp1763_hcd *hcd_to_priv(struct usb_hcd *hcd)
+{
+ return (struct isp1763_hcd *) (hcd->hcd_priv);
+}
+
+/* Section 2.2 Host Controller Capability Registers */
+#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
+#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
+#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
+#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
+#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
+#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
+#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
+
+/* Section 2.3 Host Controller Operational Registers */
+#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
+#define CMD_RESET (1<<1) /* reset HC not bus */
+#define CMD_RUN (1<<0) /* start/stop HC */
+#define STS_PCD (1<<2) /* port change detect */
+#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
+
+#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
+#define PORT_POWER (1<<12) /* true: has power (see PPC) */
+#define PORT_USB11(x) (((x) & (3 << 10)) == (1 << 10)) /* USB 1.1 device */
+#define PORT_RESET (1<<8) /* reset port */
+#define PORT_SUSPEND (1<<7) /* suspend port */
+#define PORT_RESUME (1<<6) /* resume it */
+#define PORT_PE (1<<2) /* port enable */
+#define PORT_CSC (1<<1) /* connect status change */
+#define PORT_CONNECT (1<<0) /* device connected */
+#define PORT_RWC_BITS (PORT_CSC)
+
+/* isp1763 does not have HCCPARAMS and HCSPARAMS, use hardcoded values here */
+#define HCS_HARDCODE (1 | (1 << 4)) /* Port Power Control */
+#define HCC_HARDCODE (1 << 1) /* Programmable Frame List */
+
+struct isp1763_qtd {
+ u8 packet_type;
+ void *data_buffer;
+ u32 payload_addr;
+
+ /* the rest is HCD-private */
+ struct list_head qtd_list;
+ struct urb *urb;
+ size_t length;
+ size_t actual_length;
+
+ /* QTD_ENQUEUED: waiting for transfer (inactive) */
+ /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
+ /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
+ interrupt handler may touch this qtd! */
+ /* QTD_XFER_COMPLETE: payload has been transferred successfully */
+ /* QTD_RETIRE: transfer error/abort qtd */
+#define QTD_ENQUEUED 0
+#define QTD_PAYLOAD_ALLOC 1
+#define QTD_XFER_STARTED 2
+#define QTD_XFER_COMPLETE 3
+#define QTD_RETIRE 4
+ u32 status;
+};
+
+/* Queue head, one for each active endpoint */
+struct isp1763_qh {
+ struct list_head qh_list;
+ struct list_head qtd_list;
+ u32 toggle;
+ u32 ping;
+ int slot;
+ int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */
+};
+
+struct urb_listitem {
+ struct list_head urb_list;
+ struct urb *urb;
+};
+
+/*
+ * Access functions for isp1763 registers
+ */
+static u32 reg_read32(void __iomem *base, u32 reg)
+{
+ return readl(base + reg);
+}
+
+static void reg_write32(void __iomem *base, u32 reg, u32 val)
+{
+ writel(val, base + reg);
+}
+
+static u16 reg_read16(void __iomem *base, u16 reg)
+{
+ return readw(base + reg);
+}
+
+static void reg_write16(void __iomem *base, u16 reg, u16 val)
+{
+ writew(val, base + reg);
+}
+
+/*
+ * Read from the memory space of the device (PTD and Payload)
+ *
+ * base : the device base address
+ * srcaddr : the source (start) address where the data reside on the hcd device
+ * dstptr : the destination where we want to store the data
+ * bytes : the amount of data in bytes
+ *
+ * NOTE: isp1763 does not have direct memory maped access with dual banks
+ * for ptd and payload space like the isp1760.
+ */
+static void isp1763_read_mem(void __iomem *base,
+ u16 srcaddr, u16 *dstptr, u32 bytes)
+{
+ /* Write the starting device address to the hcd memory register */
+ reg_write16(base, HC_MEMORY_REG, srcaddr);
+ ndelay(100); /* Delay between consecutive access */
+
+ /* As long there are at least 16-bit to read ... */
+ while (bytes >= 2) {
+ *dstptr = __raw_readw(base + HC_DATA_REG);
+ bytes -= 2;
+ dstptr++;
+ }
+
+ /* If there are no more bytes to read, return */
+ if (bytes <= 0)
+ return;
+
+ *((u8 *)dstptr) = (u8)(readw(base + HC_DATA_REG) & 0xFF);
+}
+
+/*
+ * Write to the memory space of the device (PTD and Payload)
+ *
+ * base : the device base address
+ * dstaddr : the destination (start) address where data is to be written
+ * src : the source of the data we want to write
+ * bytes : the amount of data in bytes
+ *
+ * NOTE: isp1763 does not have direct memory maped access with dual banks
+ * for ptd and payload space like the isp1760.
+ */
+static void isp1763_write_mem(void __iomem *base, u16 dstaddr, u16 *src,
+ u32 bytes)
+{
+ /* Write the starting device address to the hcd memory register */
+ reg_write16(base, HC_MEMORY_REG, dstaddr);
+ ndelay(100); /* Delay between consecutive access */
+
+ while (bytes >= 2) {
+ /* Get and write the data; then adjust the data ptr and len */
+ __raw_writew(*src, base + HC_DATA_REG);
+ bytes -= 2;
+ src++;
+ }
+
+ /* If there are no more bytes to process, return */
+ if (bytes <= 0)
+ return;
+
+ /*
+ * The only way to get here is if there is a single byte left,
+ * get it and write it to the data reg;
+ */
+ writew(*((u8 *)src), base + HC_DATA_REG);
+}
+
+/*
+ * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET,
+ * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than NUM_OF_PTD.
+ */
+static void ptd_read(void __iomem *base, u16 ptd_offset, u16 slot,
+ struct ptd *ptd)
+{
+ struct ptd temp_ptd;
+
+ isp1763_read_mem(base, (u16)(ptd_offset + slot*sizeof(struct ptd)),
+ (u16 *)&temp_ptd, sizeof(struct ptd));
+
+ /* Normalize the data obtained */
+ ptd->dw0 = le32_to_cpu(temp_ptd.dw0);
+ ptd->dw1 = le32_to_cpu(temp_ptd.dw1);
+ ptd->dw2 = le32_to_cpu(temp_ptd.dw2);
+ ptd->dw3 = le32_to_cpu(temp_ptd.dw3);
+ ptd->dw4 = le32_to_cpu(temp_ptd.dw4);
+ ptd->dw5 = le32_to_cpu(temp_ptd.dw5);
+ ptd->dw6 = le32_to_cpu(temp_ptd.dw6);
+ ptd->dw7 = le32_to_cpu(temp_ptd.dw7);
+
+}
+
+static void ptd_write(void __iomem *base, u16 ptd_offset, u16 slot,
+ struct ptd *temp_ptd)
+{
+ u16 offset;
+ struct ptd ptd;
+
+ offset = ptd_offset + slot*sizeof(struct ptd);
+
+ /* Normalize the data to be written */
+ ptd.dw0 = cpu_to_le32(temp_ptd->dw0);
+ ptd.dw1 = cpu_to_le32(temp_ptd->dw1);
+ ptd.dw2 = cpu_to_le32(temp_ptd->dw2);
+ ptd.dw3 = cpu_to_le32(temp_ptd->dw3);
+ ptd.dw4 = cpu_to_le32(temp_ptd->dw4);
+ ptd.dw5 = cpu_to_le32(temp_ptd->dw5);
+ ptd.dw6 = cpu_to_le32(temp_ptd->dw6);
+ ptd.dw7 = cpu_to_le32(temp_ptd->dw7);
+
+ isp1763_write_mem(base, (u16)(offset + sizeof(ptd.dw0)),
+ (u16 *)&(ptd.dw1), 7*sizeof(ptd.dw1));
+
+ /* Make sure dw0 gets written last (after other dw's and after payload)
+ since it contains the enable bit */
+ wmb();
+
+ isp1763_write_mem(base, offset, (u16 *)&(ptd.dw0), sizeof(ptd.dw0));
+}
+
+/* memory management of the 20kb payload on the chip from 0x1000 to 0x5fff */
+static void init_memory(struct isp1763_hcd *priv)
+{
+ int i, curr;
+ u32 payload_addr;
+
+ payload_addr = PAYLOAD_OFFSET;
+ for (i = 0; i < BLOCK_1_NUM; i++) {
+ priv->memory_pool[i].start = payload_addr;
+ priv->memory_pool[i].size = BLOCK_1_SIZE;
+ priv->memory_pool[i].free = 1;
+ payload_addr += priv->memory_pool[i].size;
+ }
+
+ curr = i;
+ for (i = 0; i < BLOCK_2_NUM; i++) {
+ priv->memory_pool[curr + i].start = payload_addr;
+ priv->memory_pool[curr + i].size = BLOCK_2_SIZE;
+ priv->memory_pool[curr + i].free = 1;
+ payload_addr += priv->memory_pool[curr + i].size;
+ }
+
+ curr = i;
+ for (i = 0; i < BLOCK_3_NUM; i++) {
+ priv->memory_pool[curr + i].start = payload_addr;
+ priv->memory_pool[curr + i].size = BLOCK_3_SIZE;
+ priv->memory_pool[curr + i].free = 1;
+ payload_addr += priv->memory_pool[curr + i].size;
+ }
+
+ WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
+}
+
+static void alloc_mem(struct usb_hcd *hcd, struct isp1763_qtd *qtd)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ int i;
+
+ WARN_ON(qtd->payload_addr);
+
+ if (!qtd->length)
+ return;
+
+ for (i = 0; i < BLOCKS; i++) {
+ if (priv->memory_pool[i].size >= qtd->length &&
+ priv->memory_pool[i].free) {
+
+ priv->memory_pool[i].free = 0;
+ qtd->payload_addr = priv->memory_pool[i].start;
+ return;
+ }
+ }
+}
+
+static void free_mem(struct usb_hcd *hcd, struct isp1763_qtd *qtd)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ int i;
+
+ if (!qtd->payload_addr)
+ return;
+
+ for (i = 0; i < BLOCKS; i++) {
+ if (priv->memory_pool[i].start == qtd->payload_addr) {
+ WARN_ON(priv->memory_pool[i].free);
+ priv->memory_pool[i].free = 1;
+ qtd->payload_addr = 0;
+ return;
+ }
+ }
+
+ dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
+ __func__, qtd->payload_addr);
+ WARN_ON(1);
+ qtd->payload_addr = 0;
+}
+
+/* WARNING!
+ * This handshake() function should only be used for 32-bit registers
+ * All the accesses so far seems okay for isp1763, since they only access the
+ * standard EHCI regs, which are all 32-bit.
+ */
+static int handshake(struct usb_hcd *hcd, u32 reg,
+ u32 mask, u32 done, int usec)
+{
+ u32 result;
+
+ do {
+ result = reg_read32(hcd->regs, reg);
+ if (result == ~0)
+ return -ENODEV;
+ result &= mask;
+ if (result == done)
+ return 0;
+ udelay(1);
+ usec--;
+ } while (usec > 0);
+ return -ETIMEDOUT;
+}
+
+/* reset a non-running (STS_HALT == 1) controller */
+static int ehci_reset(struct usb_hcd *hcd)
+{
+ int retval;
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ u32 command = reg_read32(hcd->regs, HC_USBCMD);
+
+ command |= CMD_RESET;
+ reg_write32(hcd->regs, HC_USBCMD, command);
+ hcd->state = HC_STATE_HALT;
+ priv->next_statechange = jiffies;
+ retval = handshake(hcd, HC_USBCMD,
+ CMD_RESET, 0, 250 * 1000);
+ return retval;
+}
+
+static struct isp1763_qh *qh_alloc(gfp_t flags)
+{
+ struct isp1763_qh *qh;
+
+ qh = kmem_cache_zalloc(qh_cachep, flags);
+ if (!qh)
+ return NULL;
+
+ INIT_LIST_HEAD(&qh->qh_list);
+ INIT_LIST_HEAD(&qh->qtd_list);
+ qh->slot = -1;
+
+ return qh;
+}
+
+static void qh_free(struct isp1763_qh *qh)
+{
+ WARN_ON(!list_empty(&qh->qtd_list));
+ WARN_ON(qh->slot > -1);
+ kmem_cache_free(qh_cachep, qh);
+}
+
+/* one-time init, only for memory state */
+static int priv_init(struct usb_hcd *hcd)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ u32 hcc_params = HCC_HARDCODE; /* Use hardcoded value */
+ int i;
+
+ spin_lock_init(&priv->lock);
+
+ for (i = 0; i < QH_END; i++)
+ INIT_LIST_HEAD(&priv->qh_list[i]);
+
+ /*
+ * hw default: 1K periodic list heads, one per frame.
+ * periodic_size can shrink by USBCMD update if hcc_params allows.
+ */
+ priv->periodic_size = DEFAULT_I_TDPS;
+
+ /* full frame cache */
+ if (HCC_ISOC_CACHE(hcc_params))
+ priv->i_thresh = 8;
+ else /* N microframes cached */
+ priv->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
+
+ return 0;
+}
+
+static int isp1763_hc_setup(struct usb_hcd *hcd)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ int result;
+ u16 scratch, hwmode, swreset;
+
+ /* low-level chip reset */
+ if (gpio_is_valid(priv->rst_gpio)) {
+ unsigned int rst_lvl;
+
+ rst_lvl = (priv->devflags &
+ ISP1763_FLAG_RESET_ACTIVE_HIGH) ? 1 : 0;
+
+ gpio_set_value(priv->rst_gpio, rst_lvl);
+ mdelay(50);
+ gpio_set_value(priv->rst_gpio, !rst_lvl);
+ }
+
+ /* Setup HW Mode Control: Initialized to HW default of 0x0000 */
+ hwmode = 0;
+
+ if (priv->devflags & ISP1763_FLAG_BUS_WIDTH_8)
+ hwmode |= HW_DATA_BUS_8BIT;
+ if (priv->devflags & ISP1763_FLAG_DACK_POL_HIGH)
+ hwmode |= HW_DACK_POL_HIGH;
+ if (priv->devflags & ISP1763_FLAG_DREQ_POL_HIGH)
+ hwmode |= HW_DREQ_POL_HIGH;
+ if (priv->devflags & ISP1763_FLAG_INTR_POL_HIGH)
+ hwmode |= HW_INTR_HIGH_ACT;
+ if (priv->devflags & ISP1763_FLAG_INTR_EDGE_TRIG)
+ hwmode |= HW_INTR_EDGE_TRIG;
+
+ pr_info("%s: devflags 0x%x hwmode 0x%x\n", __func__,
+ priv->devflags, hwmode);
+
+ /* Programming manual - Host controller register initialization step 1:
+ *
+ * Read the Chip ID register a few times to stabilize the host
+ * controller access. Delays were added before and after the dummy reads
+ * to allow the bus to settle. 2x the specified delays are used because
+ * the spec value works marginally.
+ */
+ mdelay(10); /* Delay for: reset to first dummy read operation */
+ /* Dummy read(s) to stabilize host controller access */
+ scratch = reg_read16(hcd->regs, HC_CHIP_ID_REG);
+ scratch = reg_read16(hcd->regs, HC_CHIP_ID_REG);
+ scratch = reg_read16(hcd->regs, HC_CHIP_ID_REG);
+ mdelay(20); /* 2x Delay for: dummy read to first valid read operation */
+
+ /* NOTE: The rest of the config steps is out of order with the
+ * isp1763 programming manual; but same order as isp1760 driver.
+ */
+
+ /*
+ * We have to set this first in case we're in 8-bit mode.
+ * Write it twice to ensure correct upper bits if working in 8-bit mode.
+ */
+ reg_write16(hcd->regs, HC_HW_MODE_CTRL, hwmode);
+ reg_write16(hcd->regs, HC_HW_MODE_CTRL, hwmode);
+
+ /* Write a test patten into the scratch register and reread it */
+ reg_write16(hcd->regs, HC_SCRATCH_REG, 0xabcd);
+
+ ndelay(100); /* Delay between back-to-back write and read access */
+ scratch = reg_read16(hcd->regs, HC_SCRATCH_REG);
+ if (scratch != 0xabcd) {
+ dev_err(hcd->self.controller,
+ "Scratch test failed [0x%04x != 0xabcd]\n", scratch);
+ return -ENODEV;
+ }
+
+ /* pre reset */
+ reg_write16(hcd->regs, HC_BUFFER_STATUS_REG, 0);
+ reg_write16(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
+ reg_write16(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
+ reg_write16(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
+
+ /* reset */
+ reg_write16(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
+ mdelay(100);
+ reg_write16(hcd->regs, HC_RESET_REG, SW_RESET_RESET_HC);
+ mdelay(100);
+
+ result = ehci_reset(hcd);
+ if (result)
+ return result;
+
+ /* Step 11 passed */
+ dev_info(hcd->self.controller, "bus width: %d\n",
+ (priv->devflags & ISP1763_FLAG_BUS_WIDTH_8) ? 8 : 16);
+
+ /* ATL reset */
+ swreset = reg_read16(hcd->regs, HC_RESET_REG);
+ reg_write16(hcd->regs, HC_RESET_REG, swreset | SW_RESET_RESET_ATX);
+ mdelay(10);
+ reg_write16(hcd->regs, HC_RESET_REG, swreset);
+
+ /*
+ * Re-initialize hwmode after reset, After SWRESET sequence above
+ * the settings are lost.
+ * Write it twice to ensure correct upper bits if working in 8-bit mode.
+ */
+ reg_write16(hcd->regs, HC_HW_MODE_CTRL, hwmode);
+ reg_write16(hcd->regs, HC_HW_MODE_CTRL, hwmode);
+
+ /*
+ * Enable this debug on to double check that HW_MODE
+ * settings are still sane after SWRESET
+ */
+ dev_dbg(hcd->self.controller, "hwmode: 0x%04X\n",
+ reg_read16(hcd->regs, HC_HW_MODE_CTRL));
+
+ reg_write16(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
+
+ /* Ref: isp1763 programming manual:
+ * 12. Set OTG_DISABLE (bit 10) by writing to the OTG Control register
+ * (set: E4h) and clear SW_SEL_HC_DC (bit 7) by writing to the OTG
+ * Control register (clear: E6h) to configure PORT1 in host mode.
+ *
+ * 13. Clear HC_2_DIS (bit 15) in the OTG Control register (clear: E6h)
+ * to configure PORT2 in host mode.
+ */
+ reg_write16(hcd->regs, HW_OTG_CTRL_SET, HW_OTG_CTRL_OTG_DIS);
+ reg_write16(hcd->regs, HW_OTG_CTRL_CLR, HW_OTG_CTRL_SW_SEL_HC_DC);
+ reg_write16(hcd->regs, HW_OTG_CTRL_CLR, HW_OTG_CTRL_HC_2_DIS);
+ mdelay(10);
+
+ /* This chip does not have HCSPARAMS register, use a hardcoded value. */
+ priv->hcs_params = HCS_HARDCODE;
+
+ return priv_init(hcd);
+}
+
+static u32 base_to_chip(u32 base)
+{
+ return (base - 0x400) >> 3;
+}
+
+static int last_qtd_of_urb(struct isp1763_qtd *qtd, struct isp1763_qh *qh)
+{
+ struct urb *urb;
+
+ if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
+ return 1;
+
+ urb = qtd->urb;
+ qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list);
+ return (qtd->urb != urb);
+}
+
+/* magic numbers that can affect system performance */
+#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
+#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
+#define EHCI_TUNE_RL_TT 0
+#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
+#define EHCI_TUNE_MULT_TT 1
+#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
+
+static void create_ptd_atl(struct isp1763_qh *qh,
+ struct isp1763_qtd *qtd, struct ptd *ptd)
+{
+ u32 maxpacket;
+ u32 multi;
+ u32 rl = RL_COUNTER;
+ u32 nak = NAK_COUNTER;
+
+ memset(ptd, 0, sizeof(*ptd));
+
+ /* according to 3.6.2, max packet len can not be > 0x400 */
+ maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe,
+ usb_pipeout(qtd->urb->pipe));
+ multi = 1 + ((maxpacket >> 11) & 0x3);
+ maxpacket &= 0x7ff;
+
+ /* DW0 */
+ ptd->dw0 = DW0_VALID_BIT;
+ ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
+ ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
+ ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
+
+ /* DW1 */
+ ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
+ ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
+ ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
+
+ if (usb_pipebulk(qtd->urb->pipe))
+ ptd->dw1 |= DW1_TRANS_BULK;
+ else if (usb_pipeint(qtd->urb->pipe))
+ ptd->dw1 |= DW1_TRANS_INT;
+
+ if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
+ /* split transaction */
+ ptd->dw1 |= DW1_TRANS_SPLIT;
+ if (qtd->urb->dev->speed == USB_SPEED_LOW)
+ ptd->dw1 |= DW1_SE_USB_LOSPEED;
+
+ ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
+ ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
+
+ /* SE bit for Split INT transfers */
+ if (usb_pipeint(qtd->urb->pipe) &&
+ (qtd->urb->dev->speed == USB_SPEED_LOW))
+ ptd->dw1 |= 2 << 16;
+
+ rl = 0;
+ nak = 0;
+ } else {
+ ptd->dw0 |= TO_DW0_MULTI(multi);
+ if (usb_pipecontrol(qtd->urb->pipe) ||
+ usb_pipebulk(qtd->urb->pipe))
+ ptd->dw3 |= TO_DW3_PING(qh->ping);
+ }
+ /* DW2 */
+ ptd->dw2 = 0;
+ ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
+ ptd->dw2 |= TO_DW2_RL(rl);
+
+ /* DW3 */
+ ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
+ ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
+ if (usb_pipecontrol(qtd->urb->pipe)) {
+ if (qtd->data_buffer == qtd->urb->setup_packet)
+ ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
+ else if (last_qtd_of_urb(qtd, qh))
+ ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
+ }
+
+ ptd->dw3 |= DW3_ACTIVE_BIT;
+ /* Cerr */
+ ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
+}
+
+/* Ref: ST-Ericsson isp1763 pehci driver: qtdptd.c: phci_hcd_qhint_schedule() */
+static void transform_add_int(struct isp1763_qh *qh,
+ struct isp1763_qtd *qtd, struct ptd *ptd)
+{
+ u32 usof;
+ u32 period;
+
+ /*
+ * Most of this is guessing. ISP1761 datasheet is quite unclear, and
+ * the algorithm from the original Philips driver code, which was
+ * pretty much used in this driver before as well, is quite horrendous
+ * and, i believe, incorrect. The code below follows the datasheet and
+ * USB2.0 spec as far as I can tell, and plug/unplug seems to be much
+ * more reliable this way (fingers crossed...).
+ */
+ if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
+ /* urb->interval is in units of microframes (1/8 ms) */
+ period = qtd->urb->interval >> 3;
+
+ if (qtd->urb->interval > 4)
+ usof = 0x01; /* One bit set =>
+ interval 1 ms * uFrame-match */
+ else if (qtd->urb->interval > 2)
+ usof = 0x22; /* Two bits set => interval 1/2 ms */
+ else if (qtd->urb->interval > 1)
+ usof = 0x55; /* Four bits set => interval 1/4 ms */
+ else
+ usof = 0xff; /* All bits set => interval 1/8 ms */
+ } else {
+ /* urb->interval is in units of frames (1 ms) */
+ period = qtd->urb->interval;
+ usof = 0x0f; /* Execute Start Split on any of the
+ four first uFrames */
+
+ /*
+ * First 8 bits in dw5 is uSCS and "specifies which uSOF the
+ * complete split needs to be sent. Valid only for IN." Also,
+ * "All bits can be set to one for every transfer." (p 81,
+ * ISP1763 data sheet.) 0x1c is from Philips driver. Where did
+ * that number come from? 0xff seems to work fine...
+ */
+ /* ptd->dw5 = 0x1c; */
+ /* Execute Complete Split on any uFrame */
+ ptd->dw5 = 0xff;
+ }
+
+ period = period >> 1;/* Ensure equal or shorter period than requested */
+ period &= 0xf8; /* Mask off too large values and lowest unused 3 bits */
+
+ ptd->dw2 |= period;
+ ptd->dw4 = usof;
+}
+
+static void create_ptd_int(struct isp1763_qh *qh,
+ struct isp1763_qtd *qtd, struct ptd *ptd)
+{
+ create_ptd_atl(qh, qtd, ptd);
+ transform_add_int(qh, qtd, ptd);
+}
+
+static void isp1763_urb_done(struct usb_hcd *hcd, struct urb *urb)
+__releases(priv->lock)
+__acquires(priv->lock)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+
+ if (!urb->unlinked) {
+ if (urb->status == -EINPROGRESS)
+ urb->status = 0;
+ }
+
+ if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) {
+ void *ptr;
+ for (ptr = urb->transfer_buffer;
+ ptr < urb->transfer_buffer + urb->transfer_buffer_length;
+ ptr += PAGE_SIZE)
+ flush_dcache_page(virt_to_page(ptr));
+ }
+
+ /* complete() can reenter this HCD */
+ usb_hcd_unlink_urb_from_ep(hcd, urb);
+ spin_unlock(&priv->lock);
+ usb_hcd_giveback_urb(hcd, urb, urb->status);
+ spin_lock(&priv->lock);
+}
+
+static struct isp1763_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
+ u8 packet_type)
+{
+ struct isp1763_qtd *qtd;
+
+ qtd = kmem_cache_zalloc(qtd_cachep, flags);
+ if (!qtd)
+ return NULL;
+
+ INIT_LIST_HEAD(&qtd->qtd_list);
+ qtd->urb = urb;
+ qtd->packet_type = packet_type;
+ qtd->status = QTD_ENQUEUED;
+ qtd->actual_length = 0;
+
+ return qtd;
+}
+
+static void qtd_free(struct isp1763_qtd *qtd)
+{
+ WARN_ON(qtd->payload_addr);
+ kmem_cache_free(qtd_cachep, qtd);
+}
+
+static void start_bus_transfer(struct usb_hcd *hcd, u16 ptd_offset, int slot,
+ struct slotinfo *slots, struct isp1763_qtd *qtd,
+ struct isp1763_qh *qh, struct ptd *ptd)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ int skip_map;
+
+ WARN_ON((slot < 0) || (slot > (NUM_OF_PTD - 1)));
+ WARN_ON(qtd->length && !qtd->payload_addr);
+ WARN_ON(slots[slot].qtd);
+ WARN_ON(slots[slot].qh);
+ WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
+
+ /* Make sure done map has not triggered from some unlinked transfer */
+ if (ptd_offset == ATL_PTD_OFFSET) {
+ priv->atl_done_map |= reg_read16(hcd->regs,
+ HC_ATL_PTD_DONEMAP_REG);
+ priv->atl_done_map &= ~(1 << slot);
+ } else {
+ priv->int_done_map |= reg_read16(hcd->regs,
+ HC_INT_PTD_DONEMAP_REG);
+ priv->int_done_map &= ~(1 << slot);
+ }
+
+ qh->slot = slot;
+ qtd->status = QTD_XFER_STARTED;
+ slots[slot].timestamp = jiffies;
+ slots[slot].qtd = qtd;
+ slots[slot].qh = qh;
+ ptd_write(hcd->regs, ptd_offset, slot, ptd);
+
+ if (ptd_offset == ATL_PTD_OFFSET) {
+ skip_map = reg_read16(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
+ skip_map &= ~(1 << qh->slot);
+ reg_write16(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
+ } else {
+ skip_map = reg_read16(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
+ skip_map &= ~(1 << qh->slot);
+ reg_write16(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
+ }
+}
+
+static int is_short_bulk(struct isp1763_qtd *qtd)
+{
+ return (usb_pipebulk(qtd->urb->pipe) &&
+ (qtd->actual_length < qtd->length));
+}
+
+static void collect_qtds(struct usb_hcd *hcd, struct isp1763_qh *qh,
+ struct list_head *urb_list)
+{
+ int last_qtd;
+ struct isp1763_qtd *qtd, *qtd_next;
+ struct urb_listitem *urb_listitem;
+
+ list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
+ if (qtd->status < QTD_XFER_COMPLETE)
+ break;
+
+ last_qtd = last_qtd_of_urb(qtd, qh);
+
+ if ((!last_qtd) && (qtd->status == QTD_RETIRE))
+ qtd_next->status = QTD_RETIRE;
+
+ if (qtd->status == QTD_XFER_COMPLETE) {
+ if (qtd->actual_length) {
+ switch (qtd->packet_type) {
+ case IN_PID:
+ isp1763_read_mem(hcd->regs,
+ qtd->payload_addr,
+ qtd->data_buffer,
+ qtd->actual_length);
+ /* Fall through (?) */
+ case OUT_PID:
+ qtd->urb->actual_length +=
+ qtd->actual_length;
+ /* Fall through ... */
+ case SETUP_PID:
+ break;
+ }
+ }
+
+ if (is_short_bulk(qtd)) {
+ if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
+ qtd->urb->status = -EREMOTEIO;
+ if (!last_qtd)
+ qtd_next->status = QTD_RETIRE;
+ }
+ }
+
+ if (qtd->payload_addr)
+ free_mem(hcd, qtd);
+
+ if (last_qtd) {
+ if ((qtd->status == QTD_RETIRE) &&
+ (qtd->urb->status == -EINPROGRESS))
+ qtd->urb->status = -EPIPE;
+ /* Defer calling of urb_done() since it releases lock */
+ urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
+ GFP_ATOMIC);
+ if (unlikely(!urb_listitem))
+ break; /* Try again on next call */
+ urb_listitem->urb = qtd->urb;
+ list_add_tail(&urb_listitem->urb_list, urb_list);
+ }
+
+ list_del(&qtd->qtd_list);
+ qtd_free(qtd);
+ }
+}
+
+#define ENQUEUE_DEPTH 2
+static void enqueue_qtds(struct usb_hcd *hcd, struct isp1763_qh *qh)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ int ptd_offset;
+ struct slotinfo *slots;
+ int curr_slot, free_slot;
+ int n;
+ struct ptd ptd;
+ struct isp1763_qtd *qtd;
+
+ if (unlikely(list_empty(&qh->qtd_list))) {
+ WARN_ON(1);
+ return;
+ }
+
+ /* Make sure this endpoint's TT buffer is clean before queueing ptds */
+ if (qh->tt_buffer_dirty)
+ return;
+
+ if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1763_qtd,
+ qtd_list)->urb->pipe)) {
+ ptd_offset = INT_PTD_OFFSET;
+ slots = priv->int_slots;
+ } else {
+ ptd_offset = ATL_PTD_OFFSET;
+ slots = priv->atl_slots;
+ }
+
+ free_slot = -1;
+ for (curr_slot = 0; curr_slot < NUM_OF_PTD; curr_slot++) {
+ if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
+ free_slot = curr_slot;
+ if (slots[curr_slot].qh == qh)
+ break;
+ }
+
+ n = 0;
+ list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
+ if (qtd->status == QTD_ENQUEUED) {
+ WARN_ON(qtd->payload_addr);
+ alloc_mem(hcd, qtd);
+ if ((qtd->length) && (!qtd->payload_addr))
+ break;
+
+ if ((qtd->length) &&
+ ((qtd->packet_type == SETUP_PID) ||
+ (qtd->packet_type == OUT_PID))) {
+ isp1763_write_mem(hcd->regs, qtd->payload_addr,
+ qtd->data_buffer, qtd->length);
+ }
+
+ qtd->status = QTD_PAYLOAD_ALLOC;
+ }
+
+ if (qtd->status == QTD_PAYLOAD_ALLOC) {
+/*
+ if ((curr_slot > (NUM_OF_PTD-1)) && (free_slot == -1))
+ dev_dbg(hcd->self.controller, "%s: No slot "
+ "available for transfer\n", __func__);
+*/
+ /* Start xfer for this endpoint if not already done */
+ if ((curr_slot > (NUM_OF_PTD-1)) && (free_slot > -1)) {
+ if (usb_pipeint(qtd->urb->pipe))
+ create_ptd_int(qh, qtd, &ptd);
+ else
+ create_ptd_atl(qh, qtd, &ptd);
+
+ start_bus_transfer(hcd, ptd_offset, free_slot,
+ slots, qtd, qh, &ptd);
+ curr_slot = free_slot;
+ }
+
+ n++;
+ if (n >= ENQUEUE_DEPTH)
+ break;
+ }
+ }
+}
+
+static void schedule_ptds(struct usb_hcd *hcd)
+{
+ struct isp1763_hcd *priv;
+ struct isp1763_qh *qh, *qh_next;
+ struct list_head *ep_queue;
+ LIST_HEAD(urb_list);
+ struct urb_listitem *urb_listitem, *urb_listitem_next;
+ int i;
+
+ if (!hcd) {
+ WARN_ON(1);
+ return;
+ }
+
+ priv = hcd_to_priv(hcd);
+
+ /*
+ * check finished/retired xfers, transfer payloads, call urb_done()
+ */
+ for (i = 0; i < QH_END; i++) {
+ ep_queue = &priv->qh_list[i];
+ list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
+ collect_qtds(hcd, qh, &urb_list);
+ if (list_empty(&qh->qtd_list))
+ list_del(&qh->qh_list);
+ }
+ }
+
+ list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
+ urb_list) {
+ isp1763_urb_done(hcd, urb_listitem->urb);
+ kmem_cache_free(urb_listitem_cachep, urb_listitem);
+ }
+
+ /*
+ * Schedule packets for transfer.
+ *
+ * According to USB2.0 specification:
+ *
+ * 1st prio: interrupt xfers, up to 80 % of bandwidth
+ * 2nd prio: control xfers
+ * 3rd prio: bulk xfers
+ *
+ * ... but let's use a simpler scheme here (mostly because ISP1761 doc
+ * is very unclear on how to prioritize traffic):
+ *
+ * 1) Enqueue any queued control transfers, as long as payload chip mem
+ * and PTD ATL slots are available.
+ * 2) Enqueue any queued INT transfers, as long as payload chip mem
+ * and PTD INT slots are available.
+ * 3) Enqueue any queued bulk transfers, as long as payload chip mem
+ * and PTD ATL slots are available.
+ *
+ * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
+ * conservation of chip mem and performance.
+ *
+ * I'm sure this scheme could be improved upon!
+ */
+ for (i = 0; i < QH_END; i++) {
+ ep_queue = &priv->qh_list[i];
+ list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
+ enqueue_qtds(hcd, qh);
+ }
+}
+
+#define PTD_STATE_QTD_DONE 1
+#define PTD_STATE_QTD_RELOAD 2
+#define PTD_STATE_URB_RETIRE 3
+
+static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
+ struct urb *urb)
+{
+ __dw dw4;
+ int i;
+
+ dw4 = ptd->dw4;
+ dw4 >>= 8;
+
+ /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
+ need to handle these errors? Is it done in hardware? */
+
+ if (ptd->dw3 & DW3_HALT_BIT) {
+
+ urb->status = -EPROTO; /* Default unknown error */
+
+ for (i = 0; i < 8; i++) {
+ switch (dw4 & 0x7) {
+ case INT_UNDERRUN:
+ dev_dbg(hcd->self.controller, "%s: underrun "
+ "during uFrame %d\n",
+ __func__, i);
+ urb->status = -ECOMM; /* Could not write data */
+ break;
+ case INT_EXACT:
+ dev_dbg(hcd->self.controller, "%s: transaction "
+ "error during uFrame %d\n",
+ __func__, i);
+ urb->status = -EPROTO; /* timeout, bad CRC, PID
+ error etc. */
+ break;
+ case INT_BABBLE:
+ dev_dbg(hcd->self.controller, "%s: babble "
+ "error during uFrame %d\n",
+ __func__, i);
+ urb->status = -EOVERFLOW;
+ break;
+ }
+ dw4 >>= 3;
+ }
+
+ return PTD_STATE_URB_RETIRE;
+ }
+
+ return PTD_STATE_QTD_DONE;
+}
+
+static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
+ struct urb *urb)
+{
+ WARN_ON(!ptd);
+ if (ptd->dw3 & DW3_HALT_BIT) {
+ if (ptd->dw3 & DW3_BABBLE_BIT)
+ urb->status = -EOVERFLOW;
+ else if (FROM_DW3_CERR(ptd->dw3))
+ urb->status = -EPIPE; /* Stall */
+ else if (ptd->dw3 & DW3_ERROR_BIT)
+ urb->status = -EPROTO; /* XactErr */
+ else
+ urb->status = -EPROTO; /* Unknown */
+/*
+ dev_dbg(hcd->self.controller, "%s: ptd error:\n"
+ " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
+ " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
+ __func__,
+ ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
+ ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
+*/
+ return PTD_STATE_URB_RETIRE;
+ }
+
+ if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
+ /* Transfer Error, *but* active and no HALT -> reload */
+ dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
+ return PTD_STATE_QTD_RELOAD;
+ }
+
+ if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
+ /*
+ * NAKs are handled in HW by the chip. Usually if the
+ * device is not able to send data fast enough.
+ * This happens mostly on slower hardware.
+ */
+ return PTD_STATE_QTD_RELOAD;
+ }
+
+ return PTD_STATE_QTD_DONE;
+}
+
+static void handle_done_ptds(struct usb_hcd *hcd)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ struct ptd ptd;
+ struct isp1763_qh *qh;
+ int slot;
+ int state;
+ struct slotinfo *slots;
+ u32 ptd_offset;
+ struct isp1763_qtd *qtd;
+ u16 modified;
+ int skip_map;
+
+ skip_map = reg_read16(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
+ priv->int_done_map &= ~skip_map;
+ skip_map = reg_read16(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
+ priv->atl_done_map &= ~skip_map;
+
+ modified = priv->int_done_map || priv->atl_done_map;
+
+ while (priv->int_done_map || priv->atl_done_map) {
+ if (priv->int_done_map) {
+ /* INT ptd */
+ slot = __ffs((u32)priv->int_done_map);
+ priv->int_done_map &= ~(1 << slot);
+ slots = priv->int_slots;
+ /* This should not trigger, and could be removed if
+ noone have any problems with it triggering: */
+ if (!slots[slot].qh) {
+ WARN_ON(1);
+ continue;
+ }
+ ptd_offset = INT_PTD_OFFSET;
+ ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
+ state = check_int_transfer(hcd, &ptd,
+ slots[slot].qtd->urb);
+ } else {
+ /* ATL ptd */
+ slot = __ffs((u32)priv->atl_done_map);
+ priv->atl_done_map &= ~(1 << slot);
+ slots = priv->atl_slots;
+ /* This should not trigger, and could be removed if
+ noone have any problems with it triggering: */
+ if (!slots[slot].qh) {
+ WARN_ON(1);
+ continue;
+ }
+ ptd_offset = ATL_PTD_OFFSET;
+ ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
+ state = check_atl_transfer(hcd, &ptd,
+ slots[slot].qtd->urb);
+ }
+
+ qtd = slots[slot].qtd;
+ slots[slot].qtd = NULL;
+ qh = slots[slot].qh;
+ slots[slot].qh = NULL;
+ qh->slot = -1;
+
+ WARN_ON(qtd->status != QTD_XFER_STARTED);
+
+ switch (state) {
+ case PTD_STATE_QTD_DONE:
+ if ((usb_pipeint(qtd->urb->pipe)) &&
+ (qtd->urb->dev->speed != USB_SPEED_HIGH))
+ qtd->actual_length =
+ FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
+ else
+ qtd->actual_length =
+ FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
+
+ qtd->status = QTD_XFER_COMPLETE;
+ if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
+ is_short_bulk(qtd))
+ qtd = NULL;
+ else
+ qtd = list_entry(qtd->qtd_list.next,
+ typeof(*qtd), qtd_list);
+
+ qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
+ qh->ping = FROM_DW3_PING(ptd.dw3);
+ break;
+
+ case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
+ qtd->status = QTD_PAYLOAD_ALLOC;
+ ptd.dw0 |= DW0_VALID_BIT;
+ /* RL counter = ERR counter */
+ ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
+ ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
+ ptd.dw3 &= ~TO_DW3_CERR(3);
+ ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
+ qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
+ qh->ping = FROM_DW3_PING(ptd.dw3);
+ break;
+
+ case PTD_STATE_URB_RETIRE:
+ qtd->status = QTD_RETIRE;
+ if ((qtd->urb->dev->speed != USB_SPEED_HIGH) &&
+ (qtd->urb->status != -EPIPE) &&
+ (qtd->urb->status != -EREMOTEIO)) {
+ qh->tt_buffer_dirty = 1;
+ if (usb_hub_clear_tt_buffer(qtd->urb))
+ /* Clear failed; let's hope things work
+ anyway */
+ qh->tt_buffer_dirty = 0;
+ }
+ qtd = NULL;
+ qh->toggle = 0;
+ qh->ping = 0;
+ break;
+
+ default:
+ WARN_ON(1);
+ continue;
+ }
+
+ if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
+ if (slots == priv->int_slots) {
+ if (state == PTD_STATE_QTD_RELOAD)
+ dev_err(hcd->self.controller,
+ "%s: PTD_STATE_QTD_RELOAD on "
+ "interrupt packet\n", __func__);
+ if (state != PTD_STATE_QTD_RELOAD)
+ create_ptd_int(qh, qtd, &ptd);
+ } else {
+ if (state != PTD_STATE_QTD_RELOAD)
+ create_ptd_atl(qh, qtd, &ptd);
+ }
+
+ start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
+ qh, &ptd);
+ }
+ }
+
+ if (modified)
+ schedule_ptds(hcd);
+}
+
+static irqreturn_t isp1763_irq(struct usb_hcd *hcd)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ u16 imask;
+ irqreturn_t irqret = IRQ_NONE;
+
+ spin_lock(&priv->lock);
+
+ if (!(hcd->state & HC_STATE_RUNNING))
+ goto leave;
+
+ imask = reg_read16(hcd->regs, HC_INTERRUPT_REG);
+ if (unlikely(!imask))
+ goto leave;
+ reg_write16(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
+
+ priv->int_done_map |= reg_read16(hcd->regs, HC_INT_PTD_DONEMAP_REG);
+ priv->atl_done_map |= reg_read16(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
+
+ handle_done_ptds(hcd);
+
+ irqret = IRQ_HANDLED;
+leave:
+ spin_unlock(&priv->lock);
+
+ return irqret;
+}
+
+/*
+ * Workaround for problem described in chip errata 2:
+ *
+ * Sometimes interrupts are not generated when ATL (not INT?) completion occurs.
+ * One solution suggested in the errata is to use SOF interrupts _instead_of_
+ * ATL done interrupts (the "instead of" might be important since it seems
+ * enabling ATL interrupts also causes the chip to sometimes - rarely - "forget"
+ * to set the PTD's done bit in addition to not generating an interrupt!).
+ *
+ * So if we use SOF + ATL interrupts, we sometimes get stale PTDs since their
+ * done bit is not being set. This is bad - it blocks the endpoint until reboot.
+ *
+ * If we use SOF interrupts only, we get latency between ptd completion and the
+ * actual handling. This is very noticeable in testusb runs which takes several
+ * minutes longer without ATL interrupts.
+ *
+ * A better solution is to run the code below every SLOT_CHECK_PERIOD ms. If it
+ * finds active ATL slots which are older than SLOT_TIMEOUT ms, it checks the
+ * slot's ACTIVE and VALID bits. If these are not set, the ptd is considered
+ * completed and its done map bit is set.
+ *
+ * The values of SLOT_TIMEOUT and SLOT_CHECK_PERIOD have been arbitrarily chosen
+ * not to cause too much lag when this HW bug occurs, while still hopefully
+ * ensuring that the check does not falsely trigger.
+ */
+#define SLOT_TIMEOUT 300
+#define SLOT_CHECK_PERIOD 200
+static struct timer_list errata2_timer;
+
+static void errata2_function(unsigned long data)
+{
+ struct usb_hcd *hcd = (struct usb_hcd *) data;
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ u16 slot;
+ struct ptd ptd;
+ unsigned long spinflags;
+
+ spin_lock_irqsave(&priv->lock, spinflags);
+
+ for (slot = 0; slot < NUM_OF_PTD; slot++)
+ if (priv->atl_slots[slot].qh && time_after(jiffies,
+ priv->atl_slots[slot].timestamp +
+ SLOT_TIMEOUT * HZ / 1000)) {
+ ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
+ if (!FROM_DW0_VALID(ptd.dw0) &&
+ !FROM_DW3_ACTIVE(ptd.dw3))
+ priv->atl_done_map |= 1 << slot;
+ }
+
+ if (priv->atl_done_map)
+ handle_done_ptds(hcd);
+
+ spin_unlock_irqrestore(&priv->lock, spinflags);
+
+ errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
+ add_timer(&errata2_timer);
+}
+
+static int isp1763_run(struct usb_hcd *hcd)
+{
+ int retval;
+ u32 temp;
+ u32 command;
+ u32 chipid;
+
+ hcd->uses_new_polling = 1;
+
+ hcd->state = HC_STATE_RUNNING;
+
+ /* Set PTD interrupt AND & OR maps */
+ reg_write16(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
+ reg_write16(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffff);
+ reg_write16(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
+ reg_write16(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffff);
+ reg_write16(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
+ reg_write16(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffff);
+ /* step 23 passed */
+
+ temp = reg_read16(hcd->regs, HC_HW_MODE_CTRL);
+ reg_write16(hcd->regs, HC_HW_MODE_CTRL, temp | HW_GLOBAL_INTR_EN);
+
+ command = reg_read32(hcd->regs, HC_USBCMD);
+ command &= ~(CMD_LRESET|CMD_RESET);
+ command |= CMD_RUN;
+ reg_write32(hcd->regs, HC_USBCMD, command);
+
+ retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
+ if (retval)
+ return retval;
+
+ /*
+ * XXX
+ * Spec says to write FLAG_CF as last config action, priv code grabs
+ * the semaphore while doing so.
+ */
+ down_write(&ehci_cf_port_reset_rwsem);
+ reg_write32(hcd->regs, HC_CONFIGFLAG, FLAG_CF);
+
+ retval = handshake(hcd, HC_CONFIGFLAG, FLAG_CF, FLAG_CF, 250 * 1000);
+ up_write(&ehci_cf_port_reset_rwsem);
+ if (retval)
+ return retval;
+
+ init_timer(&errata2_timer);
+ errata2_timer.function = errata2_function;
+ errata2_timer.data = (unsigned long) hcd;
+ errata2_timer.expires = jiffies + SLOT_CHECK_PERIOD * HZ / 1000;
+ add_timer(&errata2_timer);
+
+ chipid = reg_read32(hcd->regs, HC_CHIP_ID_REG);
+ dev_info(hcd->self.controller, "USB ISP %04x HW rev. %d started\n",
+ ((chipid & 0x00ffff00) >> 8), (chipid & 0x000000ff));
+
+ /* PTD Register Init Part 2, Step 28 */
+
+ /* Setup registers controlling PTD checking */
+ reg_write16(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x8000);
+ reg_write16(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x8000);
+ reg_write16(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x0001);
+ reg_write16(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffff);
+ reg_write16(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffff);
+ reg_write16(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffff);
+ reg_write16(hcd->regs, HC_BUFFER_STATUS_REG,
+ ATL_BUF_FILL | INT_BUF_FILL);
+
+ /* GRR this is run-once init(), being done every time the HC starts.
+ * So long as they're part of class devices, we can't do it init()
+ * since the class device isn't created that early.
+ */
+ return 0;
+}
+
+static int qtd_fill(struct isp1763_qtd *qtd, void *databuffer, size_t len)
+{
+ qtd->data_buffer = databuffer;
+
+ if (len > MAX_PAYLOAD_SIZE)
+ len = MAX_PAYLOAD_SIZE;
+ qtd->length = len;
+
+ return qtd->length;
+}
+
+static void qtd_list_free(struct list_head *qtd_list)
+{
+ struct isp1763_qtd *qtd, *qtd_next;
+
+ list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
+ list_del(&qtd->qtd_list);
+ qtd_free(qtd);
+ }
+}
+
+/*
+ * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
+ * Also calculate the PID type (SETUP/IN/OUT) for each packet.
+ */
+#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
+static void packetize_urb(struct usb_hcd *hcd,
+ struct urb *urb, struct list_head *head, gfp_t flags)
+{
+ struct isp1763_qtd *qtd;
+ void *buf;
+ int len, maxpacketsize;
+ u8 packet_type;
+
+ /*
+ * URBs map to sequences of QTDs: one logical transaction
+ */
+ if (!urb->transfer_buffer && urb->transfer_buffer_length) {
+ /* XXX This looks like usb storage / SCSI bug */
+ dev_err(hcd->self.controller,
+ "buf is null, dma is %08lx len is %d\n",
+ (long unsigned)urb->transfer_dma,
+ urb->transfer_buffer_length);
+ WARN_ON(1);
+ }
+
+ if (usb_pipein(urb->pipe))
+ packet_type = IN_PID;
+ else
+ packet_type = OUT_PID;
+
+ if (usb_pipecontrol(urb->pipe)) {
+ qtd = qtd_alloc(flags, urb, SETUP_PID);
+ if (!qtd)
+ goto cleanup;
+ qtd_fill(qtd, urb->setup_packet,
+ sizeof(struct usb_ctrlrequest));
+ list_add_tail(&qtd->qtd_list, head);
+
+ /* for zero length DATA stages, STATUS is always IN */
+ if (urb->transfer_buffer_length == 0)
+ packet_type = IN_PID;
+ }
+
+ maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
+ usb_pipeout(urb->pipe)));
+
+ /*
+ * buffer gets wrapped in one or more qtds;
+ * last one may be "short" (including zero len)
+ * and may serve as a control status ack
+ */
+ buf = urb->transfer_buffer;
+ len = urb->transfer_buffer_length;
+
+ for (;;) {
+ int this_qtd_len;
+
+ qtd = qtd_alloc(flags, urb, packet_type);
+ if (!qtd)
+ goto cleanup;
+ this_qtd_len = qtd_fill(qtd, buf, len);
+ list_add_tail(&qtd->qtd_list, head);
+
+ len -= this_qtd_len;
+ buf += this_qtd_len;
+
+ if (len <= 0)
+ break;
+ }
+
+ /*
+ * control requests may need a terminating data "status" ack;
+ * bulk ones may need a terminating short packet (zero length).
+ */
+ if (urb->transfer_buffer_length != 0) {
+ int one_more = 0;
+
+ if (usb_pipecontrol(urb->pipe)) {
+ one_more = 1;
+ if (packet_type == IN_PID)
+ packet_type = OUT_PID;
+ else
+ packet_type = IN_PID;
+ } else if (usb_pipebulk(urb->pipe)
+ && (urb->transfer_flags & URB_ZERO_PACKET)
+ && !(urb->transfer_buffer_length %
+ maxpacketsize)) {
+ one_more = 1;
+ }
+ if (one_more) {
+ qtd = qtd_alloc(flags, urb, packet_type);
+ if (!qtd)
+ goto cleanup;
+
+ /* never any data in such packets */
+ qtd_fill(qtd, NULL, 0);
+ list_add_tail(&qtd->qtd_list, head);
+ }
+ }
+
+ return;
+
+cleanup:
+ qtd_list_free(head);
+}
+
+static int isp1763_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
+ gfp_t mem_flags)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ struct list_head *ep_queue;
+ struct isp1763_qh *qh, *qhit;
+ unsigned long spinflags;
+ LIST_HEAD(new_qtds);
+ int retval;
+ int qh_in_queue;
+
+ switch (usb_pipetype(urb->pipe)) {
+ case PIPE_CONTROL:
+ ep_queue = &priv->qh_list[QH_CONTROL];
+ break;
+ case PIPE_BULK:
+ ep_queue = &priv->qh_list[QH_BULK];
+ break;
+ case PIPE_INTERRUPT:
+ if (urb->interval < 0)
+ return -EINVAL;
+ /* FIXME: Check bandwidth */
+ ep_queue = &priv->qh_list[QH_INTERRUPT];
+ break;
+ case PIPE_ISOCHRONOUS:
+ dev_err(hcd->self.controller, "%s: isochronous USB packets "
+ "not yet supported\n",
+ __func__);
+ return -EPIPE;
+ default:
+ dev_err(hcd->self.controller, "%s: unknown pipe type\n",
+ __func__);
+ return -EPIPE;
+ }
+
+ if (usb_pipein(urb->pipe))
+ urb->actual_length = 0;
+
+ packetize_urb(hcd, urb, &new_qtds, mem_flags);
+ if (list_empty(&new_qtds))
+ return -ENOMEM;
+
+ retval = 0;
+ spin_lock_irqsave(&priv->lock, spinflags);
+
+ if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+ qtd_list_free(&new_qtds);
+ retval = -ESHUTDOWN;
+ goto out;
+ }
+ retval = usb_hcd_link_urb_to_ep(hcd, urb);
+ if (retval) {
+ qtd_list_free(&new_qtds);
+ goto out;
+ }
+
+ qh = urb->ep->hcpriv;
+ if (qh) {
+ qh_in_queue = 0;
+ list_for_each_entry(qhit, ep_queue, qh_list) {
+ if (qhit == qh) {
+ qh_in_queue = 1;
+ break;
+ }
+ }
+ if (!qh_in_queue)
+ list_add_tail(&qh->qh_list, ep_queue);
+ } else {
+ qh = qh_alloc(GFP_ATOMIC);
+ if (!qh) {
+ retval = -ENOMEM;
+ usb_hcd_unlink_urb_from_ep(hcd, urb);
+ qtd_list_free(&new_qtds);
+ goto out;
+ }
+ list_add_tail(&qh->qh_list, ep_queue);
+ urb->ep->hcpriv = qh;
+ }
+
+ list_splice_tail(&new_qtds, &qh->qtd_list);
+ schedule_ptds(hcd);
+
+out:
+ spin_unlock_irqrestore(&priv->lock, spinflags);
+ return retval;
+}
+
+static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
+ struct isp1763_qh *qh)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ u16 skip_map;
+
+ WARN_ON(qh->slot == -1);
+
+ /* We need to forcefully reclaim the slot since some transfers never
+ return, e.g. interrupt transfers and NAKed bulk transfers. */
+ if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) {
+ skip_map = reg_read16(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
+ skip_map |= (1 << qh->slot);
+ reg_write16(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
+ priv->atl_slots[qh->slot].qh = NULL;
+ priv->atl_slots[qh->slot].qtd = NULL;
+ } else {
+ skip_map = reg_read16(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
+ skip_map |= (1 << qh->slot);
+ reg_write16(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
+ priv->int_slots[qh->slot].qh = NULL;
+ priv->int_slots[qh->slot].qtd = NULL;
+ }
+
+ qh->slot = -1;
+}
+
+/*
+ * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing
+ * any active transfer belonging to the urb in the process.
+ */
+static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1763_qh *qh,
+ struct isp1763_qtd *qtd)
+{
+ struct urb *urb;
+ int urb_was_running;
+
+ urb = qtd->urb;
+ urb_was_running = 0;
+ list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) {
+ if (qtd->urb != urb)
+ break;
+
+ if (qtd->status >= QTD_XFER_STARTED)
+ urb_was_running = 1;
+ if (last_qtd_of_urb(qtd, qh) &&
+ (qtd->status >= QTD_XFER_COMPLETE))
+ urb_was_running = 0;
+
+ if (qtd->status == QTD_XFER_STARTED)
+ kill_transfer(hcd, urb, qh);
+ qtd->status = QTD_RETIRE;
+ }
+
+ if ((urb->dev->speed != USB_SPEED_HIGH) && urb_was_running) {
+ qh->tt_buffer_dirty = 1;
+ if (usb_hub_clear_tt_buffer(urb))
+ /* Clear failed; let's hope things work anyway */
+ qh->tt_buffer_dirty = 0;
+ }
+}
+
+static int isp1763_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
+ int status)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ unsigned long spinflags;
+ struct isp1763_qh *qh;
+ struct isp1763_qtd *qtd;
+ int retval = 0;
+
+ spin_lock_irqsave(&priv->lock, spinflags);
+ retval = usb_hcd_check_unlink_urb(hcd, urb, status);
+ if (retval)
+ goto out;
+
+ qh = urb->ep->hcpriv;
+ if (!qh) {
+ retval = -EINVAL;
+ goto out;
+ }
+
+ list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
+ if (qtd->urb == urb) {
+ dequeue_urb_from_qtd(hcd, qh, qtd);
+ list_move(&qtd->qtd_list, &qh->qtd_list);
+ break;
+ }
+
+ urb->status = status;
+ schedule_ptds(hcd);
+
+out:
+ spin_unlock_irqrestore(&priv->lock, spinflags);
+ return retval;
+}
+
+static void isp1763_endpoint_disable(struct usb_hcd *hcd,
+ struct usb_host_endpoint *ep)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ unsigned long spinflags;
+ struct isp1763_qh *qh, *qh_iter;
+ int i;
+
+ spin_lock_irqsave(&priv->lock, spinflags);
+
+ qh = ep->hcpriv;
+ if (!qh)
+ goto out;
+
+ WARN_ON(!list_empty(&qh->qtd_list));
+
+ for (i = 0; i < QH_END; i++)
+ list_for_each_entry(qh_iter, &priv->qh_list[i], qh_list)
+ if (qh_iter == qh) {
+ list_del(&qh_iter->qh_list);
+ i = QH_END;
+ break;
+ }
+ qh_free(qh);
+ ep->hcpriv = NULL;
+
+ schedule_ptds(hcd);
+
+out:
+ spin_unlock_irqrestore(&priv->lock, spinflags);
+}
+
+static int isp1763_hub_status_data(struct usb_hcd *hcd, char *buf)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ u32 temp, status = 0;
+ u32 mask;
+ int retval = 1;
+ unsigned long flags;
+
+ /* if !USB_SUSPEND, root hub timers won't get shut down ... */
+ if (!HC_IS_RUNNING(hcd->state))
+ return 0;
+
+ /* init status to no-changes */
+ buf[0] = 0;
+ mask = PORT_CSC;
+
+ spin_lock_irqsave(&priv->lock, flags);
+ temp = reg_read32(hcd->regs, HC_PORTSC1);
+
+ if (temp & PORT_OWNER) {
+ if (temp & PORT_CSC) {
+ temp &= ~PORT_CSC;
+ reg_write32(hcd->regs, HC_PORTSC1, temp);
+ goto done;
+ }
+ }
+
+ /*
+ * Return status information even for ports with OWNER set.
+ * Otherwise khubd wouldn't see the disconnect event when a
+ * high-speed device is switched over to the companion
+ * controller by the user.
+ */
+
+ if ((temp & mask) != 0
+ || ((temp & PORT_RESUME) != 0
+ && time_after_eq(jiffies,
+ priv->reset_done))) {
+ buf[0] |= 1 << (0 + 1);
+ status = STS_PCD;
+ }
+ /* FIXME autosuspend idle root hubs */
+done:
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return status ? retval : 0;
+}
+
+static void isp1763_hub_descriptor(struct isp1763_hcd *priv,
+ struct usb_hub_descriptor *desc)
+{
+ int ports = HCS_N_PORTS(priv->hcs_params);
+ u16 temp;
+
+ desc->bDescriptorType = 0x29;
+ /* priv 1.0, 2.3.9 says 20ms max */
+ desc->bPwrOn2PwrGood = 10;
+ desc->bHubContrCurrent = 0;
+
+ desc->bNbrPorts = ports;
+ temp = 1 + (ports / 8);
+ desc->bDescLength = 7 + 2 * temp;
+
+ /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */
+ memset(&desc->u.hs.DeviceRemovable[0], 0, temp);
+ memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp);
+
+ /* per-port overcurrent reporting; no power switching */
+ temp = 0x0008;
+
+ if (HCS_PPC(priv->hcs_params))
+ /* per-port power control */
+ temp |= 0x0001;
+ else
+ /* no power switching */
+ temp |= 0x0002;
+
+
+ desc->wHubCharacteristics = cpu_to_le16(temp);
+}
+
+#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
+
+static int check_reset_complete(struct usb_hcd *hcd, int index,
+ int port_status)
+{
+ if (!(port_status & PORT_CONNECT))
+ return port_status;
+
+ /* if reset finished and it's still not enabled -- handoff */
+ if (!(port_status & PORT_PE)) {
+
+ dev_info(hcd->self.controller,
+ "port %d full speed --> companion\n",
+ index + 1);
+
+ port_status |= PORT_OWNER;
+ port_status &= ~PORT_RWC_BITS;
+ reg_write32(hcd->regs, HC_PORTSC1, port_status);
+
+ } else
+ dev_info(hcd->self.controller, "port %d high speed\n",
+ index + 1);
+
+ return port_status;
+}
+
+static int isp1763_hub_control(struct usb_hcd *hcd, u16 typeReq,
+ u16 wValue, u16 wIndex, char *buf, u16 wLength)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ int ports = HCS_N_PORTS(priv->hcs_params);
+ u32 temp, status;
+ unsigned long flags;
+ int retval = 0;
+ unsigned selector;
+
+ /*
+ * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR.
+ * HCS_INDICATOR may say we can change LEDs to off/amber/green.
+ * (track current state ourselves) ... blink for diagnostics,
+ * power, "this is the one", etc. EHCI spec supports this.
+ */
+
+ spin_lock_irqsave(&priv->lock, flags);
+ switch (typeReq) {
+ case ClearHubFeature:
+ switch (wValue) {
+ case C_HUB_LOCAL_POWER:
+ case C_HUB_OVER_CURRENT:
+ /* no hub-wide feature/status flags */
+ break;
+ default:
+ goto error;
+ }
+ break;
+ case ClearPortFeature:
+ if (!wIndex || wIndex > ports)
+ goto error;
+ wIndex--;
+ temp = reg_read32(hcd->regs, HC_PORTSC1);
+
+ /*
+ * Even if OWNER is set, so the port is owned by the
+ * companion controller, khubd needs to be able to clear
+ * the port-change status bits (especially
+ * USB_PORT_STAT_C_CONNECTION).
+ */
+
+ switch (wValue) {
+ case USB_PORT_FEAT_ENABLE:
+ reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_PE);
+ break;
+ case USB_PORT_FEAT_C_ENABLE:
+ /* XXX error? */
+ break;
+ case USB_PORT_FEAT_SUSPEND:
+ if (temp & PORT_RESET)
+ goto error;
+
+ if (temp & PORT_SUSPEND) {
+ if ((temp & PORT_PE) == 0)
+ goto error;
+ /* resume signaling for 20 msec */
+ temp &= ~(PORT_RWC_BITS);
+ reg_write32(hcd->regs, HC_PORTSC1,
+ temp | PORT_RESUME);
+ priv->reset_done = jiffies +
+ msecs_to_jiffies(20);
+ }
+ break;
+ case USB_PORT_FEAT_C_SUSPEND:
+ /* we auto-clear this feature */
+ break;
+ case USB_PORT_FEAT_POWER:
+ if (HCS_PPC(priv->hcs_params))
+ reg_write32(hcd->regs, HC_PORTSC1,
+ temp & ~PORT_POWER);
+ break;
+ case USB_PORT_FEAT_C_CONNECTION:
+ reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_CSC);
+ break;
+ case USB_PORT_FEAT_C_OVER_CURRENT:
+ /* XXX error ?*/
+ break;
+ case USB_PORT_FEAT_C_RESET:
+ /* GetPortStatus clears reset */
+ break;
+ default:
+ goto error;
+ }
+ reg_read32(hcd->regs, HC_USBCMD);
+ break;
+ case GetHubDescriptor:
+ isp1763_hub_descriptor(priv, (struct usb_hub_descriptor *)
+ buf);
+ break;
+ case GetHubStatus:
+ /* no hub-wide feature/status flags */
+ memset(buf, 0, 4);
+ break;
+ case GetPortStatus:
+ if (!wIndex || wIndex > ports)
+ goto error;
+ wIndex--;
+ status = 0;
+ temp = reg_read32(hcd->regs, HC_PORTSC1);
+
+ /* wPortChange bits */
+ if (temp & PORT_CSC)
+ status |= USB_PORT_STAT_C_CONNECTION << 16;
+
+ /* whoever resumes must GetPortStatus to complete it!! */
+ if (temp & PORT_RESUME) {
+ dev_err(hcd->self.controller, "Port resume should be skipped.\n");
+
+ /* Remote Wakeup received? */
+ if (!priv->reset_done) {
+ /* resume signaling for 20 msec */
+ priv->reset_done = jiffies
+ + msecs_to_jiffies(20);
+ /* check the port again */
+ mod_timer(&hcd->rh_timer, priv->reset_done);
+ }
+
+ /* resume completed? */
+ else if (time_after_eq(jiffies,
+ priv->reset_done)) {
+ status |= USB_PORT_STAT_C_SUSPEND << 16;
+ priv->reset_done = 0;
+
+ /* stop resume signaling */
+ temp = reg_read32(hcd->regs, HC_PORTSC1);
+ reg_write32(hcd->regs, HC_PORTSC1,
+ temp & ~(PORT_RWC_BITS | PORT_RESUME));
+ retval = handshake(hcd, HC_PORTSC1,
+ PORT_RESUME, 0, 2000 /* 2msec */);
+ if (retval != 0) {
+ dev_err(hcd->self.controller,
+ "port %d resume error %d\n",
+ wIndex + 1, retval);
+ goto error;
+ }
+ temp &= ~(PORT_SUSPEND|PORT_RESUME|(3<<10));
+ }
+ }
+
+ /* whoever resets must GetPortStatus to complete it!! */
+ if ((temp & PORT_RESET)
+ && time_after_eq(jiffies,
+ priv->reset_done)) {
+ status |= USB_PORT_STAT_C_RESET << 16;
+ priv->reset_done = 0;
+
+ /* force reset to complete */
+ reg_write32(hcd->regs, HC_PORTSC1, temp & ~PORT_RESET);
+ /* REVISIT: some hardware needs 550+ usec to clear
+ * this bit; seems too long to spin routinely...
+ */
+ retval = handshake(hcd, HC_PORTSC1,
+ PORT_RESET, 0, 750);
+ if (retval != 0) {
+ dev_err(hcd->self.controller, "port %d reset error %d\n",
+ wIndex + 1, retval);
+ goto error;
+ }
+
+ /* see what we found out */
+ temp = check_reset_complete(hcd, wIndex,
+ reg_read32(hcd->regs, HC_PORTSC1));
+ }
+ /*
+ * Even if OWNER is set, there's no harm letting khubd
+ * see the wPortStatus values (they should all be 0 except
+ * for PORT_POWER anyway).
+ */
+
+ if (temp & PORT_OWNER)
+ dev_err(hcd->self.controller, "PORT_OWNER is set\n");
+
+ if (temp & PORT_CONNECT) {
+ status |= USB_PORT_STAT_CONNECTION;
+ /* status may be from integrated TT */
+ status |= USB_PORT_STAT_HIGH_SPEED;
+ }
+ if (temp & PORT_PE)
+ status |= USB_PORT_STAT_ENABLE;
+ if (temp & (PORT_SUSPEND|PORT_RESUME))
+ status |= USB_PORT_STAT_SUSPEND;
+ if (temp & PORT_RESET)
+ status |= USB_PORT_STAT_RESET;
+ if (temp & PORT_POWER)
+ status |= USB_PORT_STAT_POWER;
+
+ put_unaligned(cpu_to_le32(status), (__le32 *) buf);
+ break;
+ case SetHubFeature:
+ switch (wValue) {
+ case C_HUB_LOCAL_POWER:
+ case C_HUB_OVER_CURRENT:
+ /* no hub-wide feature/status flags */
+ break;
+ default:
+ goto error;
+ }
+ break;
+ case SetPortFeature:
+ selector = wIndex >> 8;
+ wIndex &= 0xff;
+ if (!wIndex || wIndex > ports)
+ goto error;
+ wIndex--;
+ temp = reg_read32(hcd->regs, HC_PORTSC1);
+ if (temp & PORT_OWNER)
+ break;
+
+/* temp &= ~PORT_RWC_BITS; */
+ switch (wValue) {
+ case USB_PORT_FEAT_ENABLE:
+ reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_PE);
+ break;
+
+ case USB_PORT_FEAT_SUSPEND:
+ if ((temp & PORT_PE) == 0
+ || (temp & PORT_RESET) != 0)
+ goto error;
+
+ reg_write32(hcd->regs, HC_PORTSC1, temp | PORT_SUSPEND);
+ break;
+ case USB_PORT_FEAT_POWER:
+ if (HCS_PPC(priv->hcs_params))
+ reg_write32(hcd->regs, HC_PORTSC1,
+ temp | PORT_POWER);
+ break;
+ case USB_PORT_FEAT_RESET:
+ if (temp & PORT_RESUME)
+ goto error;
+ /* line status bits may report this as low speed,
+ * which can be fine if this root hub has a
+ * transaction translator built in.
+ */
+ if ((temp & (PORT_PE|PORT_CONNECT)) == PORT_CONNECT
+ && PORT_USB11(temp)) {
+ temp |= PORT_OWNER;
+ } else {
+ if ((temp & PORT_CONNECT) == 0) {
+ dev_err(hcd->self.controller,
+ "ERROR: Port not connected\n");
+ goto error;
+ }
+ if ((temp & PORT_POWER) == 0) {
+ dev_err(hcd->self.controller,
+ "ERROR: Port power not enabled!\n");
+ goto error;
+ }
+
+ temp |= PORT_RESET;
+ temp &= ~PORT_PE;
+
+ reg_write32(hcd->regs, HC_PORTSC1, temp);
+ /*
+ * caller must wait, then call GetPortStatus
+ * usb 2.0 spec says 50 ms resets on root
+ */
+#if 1
+ priv->reset_done = jiffies +
+ msecs_to_jiffies(50);
+#endif
+ mdelay(50);
+
+ temp &= ~PORT_RESET;
+ reg_write32(hcd->regs, HC_PORTSC1, temp);
+
+ while (reg_read32(hcd->regs, HC_PORTSC1)
+ & PORT_RESET)
+ continue;
+
+ temp |= PORT_PE;
+ reg_write32(hcd->regs, HC_PORTSC1, temp);
+ }
+ break;
+ default:
+ goto error;
+ }
+ reg_read32(hcd->regs, HC_USBCMD);
+ break;
+
+ default:
+error:
+ /* "stall" on error */
+ retval = -EPIPE;
+ }
+ spin_unlock_irqrestore(&priv->lock, flags);
+ return retval;
+}
+
+static int isp1763_get_frame(struct usb_hcd *hcd)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ u32 fr;
+
+ fr = reg_read32(hcd->regs, HC_FRINDEX);
+ return (fr >> 3) % priv->periodic_size;
+}
+
+static void isp1763_stop(struct usb_hcd *hcd)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ u16 temp;
+
+ del_timer(&errata2_timer);
+
+
+ isp1763_hub_control(hcd, ClearPortFeature, USB_PORT_FEAT_POWER, 1,
+ NULL, 0);
+ mdelay(20);
+
+ spin_lock_irq(&priv->lock);
+ ehci_reset(hcd);
+ /* Disable IRQ */
+ temp = reg_read16(hcd->regs, HC_HW_MODE_CTRL);
+ reg_write16(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
+ spin_unlock_irq(&priv->lock);
+
+ reg_write32(hcd->regs, HC_CONFIGFLAG, 0);
+}
+
+static void isp1763_shutdown(struct usb_hcd *hcd)
+{
+ u16 temp;
+ u32 command;
+
+ isp1763_stop(hcd);
+
+ temp = reg_read16(hcd->regs, HC_HW_MODE_CTRL);
+ reg_write16(hcd->regs, HC_HW_MODE_CTRL, temp &= ~HW_GLOBAL_INTR_EN);
+
+ command = reg_read32(hcd->regs, HC_USBCMD);
+ command &= ~CMD_RUN;
+ reg_write32(hcd->regs, HC_USBCMD, command);
+}
+
+static void isp1763_clear_tt_buffer_complete(struct usb_hcd *hcd,
+ struct usb_host_endpoint *ep)
+{
+ struct isp1763_hcd *priv = hcd_to_priv(hcd);
+ struct isp1763_qh *qh = ep->hcpriv;
+ unsigned long spinflags;
+
+ if (!qh)
+ return;
+
+ spin_lock_irqsave(&priv->lock, spinflags);
+ qh->tt_buffer_dirty = 0;
+ schedule_ptds(hcd);
+ spin_unlock_irqrestore(&priv->lock, spinflags);
+}
+
+
+static const struct hc_driver isp1763_hc_driver = {
+ .description = "isp1763-hcd",
+ .product_desc = "ST-Erricson ISP1763 USB Host Controller",
+ .hcd_priv_size = sizeof(struct isp1763_hcd),
+ .irq = isp1763_irq,
+ .flags = HCD_MEMORY | HCD_USB2,
+ .reset = isp1763_hc_setup,
+ .start = isp1763_run,
+ .stop = isp1763_stop,
+ .shutdown = isp1763_shutdown,
+ .urb_enqueue = isp1763_urb_enqueue,
+ .urb_dequeue = isp1763_urb_dequeue,
+ .endpoint_disable = isp1763_endpoint_disable,
+ .get_frame_number = isp1763_get_frame,
+ .hub_status_data = isp1763_hub_status_data,
+ .hub_control = isp1763_hub_control,
+ .clear_tt_buffer_complete = isp1763_clear_tt_buffer_complete,
+};
+
+int __init init_kmem_once(void)
+{
+ urb_listitem_cachep = kmem_cache_create("isp1763_urb_listitem",
+ sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
+ SLAB_MEM_SPREAD, NULL);
+
+ if (!urb_listitem_cachep)
+ return -ENOMEM;
+
+ qtd_cachep = kmem_cache_create("isp1763_qtd",
+ sizeof(struct isp1763_qtd), 0, SLAB_TEMPORARY |
+ SLAB_MEM_SPREAD, NULL);
+
+ if (!qtd_cachep)
+ return -ENOMEM;
+
+ qh_cachep = kmem_cache_create("isp1763_qh", sizeof(struct isp1763_qh),
+ 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL);
+
+ if (!qh_cachep) {
+ kmem_cache_destroy(qtd_cachep);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+void deinit_kmem_cache(void)
+{
+ kmem_cache_destroy(qtd_cachep);
+ kmem_cache_destroy(qh_cachep);
+ kmem_cache_destroy(urb_listitem_cachep);
+}
+
+/*
+ * res_start: Start of io memory region
+ * res_len : Length of io memory region
+ * irq : The (virtual) irq number
+ * irqflags : IRQ_FLAGS
+ * dev : Device structure, usually contained inside another struct
+ * busname : The bus this device belongs to
+ * devflags : Device private flags to configure quirks.
+ */
+struct usb_hcd *isp1763_register(phys_addr_t res_start,
+ resource_size_t res_len,
+ int irq, unsigned long irqflags,
+ int rst_gpio,
+ struct device *dev, const char *busname,
+ unsigned int devflags)
+{
+ struct usb_hcd *hcd;
+ struct isp1763_hcd *priv;
+ int ret;
+
+ if (usb_disabled())
+ return ERR_PTR(-ENODEV);
+
+ /* prevent usb-core allocating DMA pages */
+ dev->dma_mask = NULL;
+
+ hcd = usb_create_hcd(&isp1763_hc_driver, dev, dev_name(dev));
+ if (!hcd)
+ return ERR_PTR(-ENOMEM);
+
+ priv = hcd_to_priv(hcd);
+ priv->devflags = devflags;
+ priv->rst_gpio = rst_gpio;
+ init_memory(priv);
+
+ hcd->regs = ioremap(res_start, res_len);
+
+ if (!hcd->regs) {
+ ret = -EIO;
+ goto err_put;
+ }
+
+ hcd->irq = irq;
+ hcd->rsrc_start = res_start;
+ hcd->rsrc_len = res_len;
+
+ ret = usb_add_hcd(hcd, irq, irqflags);
+ if (ret)
+ goto err_unmap;
+
+ return hcd;
+
+err_unmap:
+ iounmap(hcd->regs);
+
+err_put:
+ usb_put_hcd(hcd);
+
+ return ERR_PTR(ret);
+}
+
diff --git a/drivers/usb/host/isp1763-hcd.h b/drivers/usb/host/isp1763-hcd.h
new file mode 100644
index 0000000..ac47992
--- /dev/null
+++ b/drivers/usb/host/isp1763-hcd.h
@@ -0,0 +1,257 @@
+#ifndef _ISP1763_HCD_H_
+#define _ISP1763_HCD_H_
+
+/* exports for isp1763-if */
+
+/* isp1763_register
+ *
+ * res_start: Start of io memory region
+ * res_len : Length of io memory region
+ * irq : The (virtual) irq number
+ * irqflags : IRQ_FLAGS
+ * dev : Device structure, usually contained inside another struct
+ * busname : The bus this device belongs to
+ * devflags : Device private flags to configure quirks.
+ */
+struct usb_hcd *isp1763_register(phys_addr_t res_start,
+ resource_size_t res_len,
+ int irq, unsigned long irqflags,
+ int rst_gpio,
+ struct device *dev, const char *busname,
+ unsigned int devflags);
+int init_kmem_once(void);
+void deinit_kmem_cache(void);
+
+/* EHCI capability registers;
+ * Vendor claims that HCCPARAMS and HCSPARAMS does not exist for isp1763,
+ * Any access to these registers need to return some hardcoded value.
+ */
+#define HC_CAPLENGTH 0x00
+#define HC_HCSPARAMS 0x04
+#define HC_HCCPARAMS 0x08
+
+/* EHCI operational registers */
+#define HC_USBCMD 0x8C
+#define HC_USBSTS 0x90
+#define HC_FRINDEX 0x98
+#define HC_CONFIGFLAG 0x9C
+#define HC_PORTSC1 0xA0
+#define HC_ISO_PTD_DONEMAP_REG 0xA4
+#define HC_ISO_PTD_SKIPMAP_REG 0xA6
+#define HC_ISO_PTD_LASTPTD_REG 0xA8
+#define HC_INT_PTD_DONEMAP_REG 0xAA
+#define HC_INT_PTD_SKIPMAP_REG 0xAC
+#define HC_INT_PTD_LASTPTD_REG 0xAE
+#define HC_ATL_PTD_DONEMAP_REG 0xB0
+#define HC_ATL_PTD_SKIPMAP_REG 0xB2
+#define HC_ATL_PTD_LASTPTD_REG 0xB4
+
+
+/* FIXME:
+ * Commented bits means that they exist in isp170, but N/A for isp1763
+*/
+
+/* Configuration Register */
+#define HC_HW_MODE_CTRL 0xB6
+/* #define ALL_ATX_RESET (1 << 31) */
+/* #define HW_ANA_DIGI_OC (1 << 15) */
+#define HW_ID_PULLUP (1 << 12)
+#define HW_DEV_DMA_EN (1 << 11)
+#define HW_COMN_INT_EN (1 << 10)
+#define HW_COMN_DMA_EN (1 << 9)
+/* #define HW_DATA_BUS_32BIT (1 << 8) */
+#define HW_DACK_POL_HIGH (1 << 6)
+#define HW_DREQ_POL_HIGH (1 << 5)
+#define HW_DATA_BUS_8BIT (1 << 4)
+#define HW_INTF_LOCK (1 << 3)
+#define HW_INTR_HIGH_ACT (1 << 2)
+#define HW_INTR_EDGE_TRIG (1 << 1)
+#define HW_GLOBAL_INTR_EN (1 << 0)
+
+#define HC_CHIP_ID_REG 0x70
+#define HC_SCRATCH_REG 0x78
+
+#define HC_RESET_REG 0xB8
+
+/* INTF_MODE[1:0] is SW_RESET[7:6] */
+#define SW_INTF_MODE_MASK 0xC0
+/* The various operation mode the chip supports */
+#define SW_INTF_MODE_NAND 0x00
+#define SW_INTF_MODE_GNRC 0x40
+#define SW_INTF_MODE_NOR 0x80
+#define SW_INTF_MODE_SRAM 0xC0
+
+#define SW_RESET_RESET_ATX (1 << 3)
+#define SW_RESET_RESET_HC (1 << 1)
+#define SW_RESET_RESET_ALL (1 << 0)
+
+#define HC_BUFFER_STATUS_REG 0xBA
+#define ISO_BUF_FILL (1 << 2)
+#define INT_BUF_FILL (1 << 1)
+#define ATL_BUF_FILL (1 << 0)
+
+#define HC_MEMORY_REG 0xC4
+#define HC_DATA_REG 0xC6
+
+/*
+ * ISP1763 does not have Port1 Control Register
+ * #define HC_PORT1_CTRL 0x374
+ * #define PORT1_POWER (3 << 3)
+ * #define PORT1_INIT1 (1 << 7)
+ * #define PORT1_INIT2 (1 << 23)
+ */
+
+#define HW_OTG_CTRL_SET 0xE4
+#define HW_OTG_CTRL_CLR 0xE6
+#define HW_OTG_CTRL_HC_2_DIS (1 << 15)
+#define HW_OTG_CTRL_OTG_DIS (1 << 10)
+#define HW_OTG_CTRL_SW_SEL_HC_DC (1 << 7)
+
+/* Interrupt Register */
+#define HC_INTERRUPT_REG 0xD4
+
+#define HC_INTERRUPT_ENABLE 0xD6
+#define HC_OTG_INT (1 << 10)
+#define HC_ISO_INT (1 << 9)
+#define HC_ATL_INT (1 << 8)
+#define HC_INTL_INT (1 << 7)
+#define HC_CLK_READY_INT (1 << 6)
+#define HC_HCSUSP_INT (1 << 5)
+#define HC_OPR_REG_INT (1 << 4)
+#define HC_EOT_INT (1 << 3)
+#define HC_SOT_INT (1 << 1)
+#define HC_USOF_INT (1 << 0) /* micro SOF interrupt */
+#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT)
+
+#define HC_ISO_IRQ_MASK_OR_REG 0xD8
+#define HC_INT_IRQ_MASK_OR_REG 0xDA
+#define HC_ATL_IRQ_MASK_OR_REG 0xDC
+#define HC_ISO_IRQ_MASK_AND_REG 0xDE
+#define HC_INT_IRQ_MASK_AND_REG 0xE0
+#define HC_ATL_IRQ_MASK_AND_REG 0xE2
+
+/* urb state*/
+#define DELETE_URB (0x0008)
+#define NO_TRANSFER_ACTIVE (0xffff)
+
+/* Philips Proprietary Transfer Descriptor (PTD) */
+typedef __u32 __bitwise __dw;
+struct ptd {
+ __dw dw0;
+ __dw dw1;
+ __dw dw2;
+ __dw dw3;
+ __dw dw4;
+ __dw dw5;
+ __dw dw6;
+ __dw dw7;
+};
+#define PTD_OFFSET 0x0400
+#define ISO_PTD_OFFSET 0x0400
+#define INT_PTD_OFFSET 0x0800
+#define ATL_PTD_OFFSET 0x0c00
+#define PAYLOAD_OFFSET 0x1000 /* size 20 kB */
+
+struct slotinfo {
+ struct isp1763_qh *qh;
+ struct isp1763_qtd *qtd;
+ unsigned long timestamp;
+};
+
+
+typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1763_qh *qh,
+ struct isp1763_qtd *qtd);
+
+/*
+ * Device flags that can vary from board to board. All of these
+ * indicate the most "atypical" case, so that a devflags of 0 is
+ * a sane default configuration.
+ */
+#define ISP1763_FLAG_BUS_WIDTH_8 0x00000002 /* 8-bit data bus width */
+#define ISP1763_FLAG_OTG_EN 0x00000004 /* Port 1 supports OTG */
+#define ISP1763_FLAG_DACK_POL_HIGH 0x00000010 /* DACK active high */
+#define ISP1763_FLAG_DREQ_POL_HIGH 0x00000020 /* DREQ active high */
+#define ISP1763_FLAG_INTR_POL_HIGH 0x00000080 /* Interrupt polarity high */
+#define ISP1763_FLAG_INTR_EDGE_TRIG 0x00000100 /* Interrupt edge triggered */
+#define ISP1763_FLAG_RESET_ACTIVE_HIGH 0x80000000 /* RESET GPIO active high */
+
+/* chip memory management */
+struct memory_chunk {
+ unsigned int start;
+ unsigned int size;
+ unsigned int free;
+};
+
+/*
+ * 20kb divided in chunks; 256 for control; 4096 for data tansfer
+ * - 8 blocks @ 256 bytes = 2KB (10%)
+ * - 2 blocks @ 1024 bytes = 2KB (10%)
+ * - 4 blocks @ 4096 bytes = 16KB (80%)
+ */
+#define BLOCK_1_NUM 8
+#define BLOCK_2_NUM 2
+#define BLOCK_3_NUM 4
+
+#define BLOCK_1_SIZE 256
+#define BLOCK_2_SIZE 1024
+#define BLOCK_3_SIZE 4096
+#define BLOCKS (BLOCK_1_NUM + BLOCK_2_NUM + BLOCK_3_NUM)
+#define MAX_PAYLOAD_SIZE BLOCK_3_SIZE
+#define PAYLOAD_AREA_SIZE 0x5000 /* 20 KB */
+
+
+/* ATL */
+/* DW0 */
+#define DW0_VALID_BIT 1
+#define FROM_DW0_VALID(x) ((x) & 0x01)
+#define TO_DW0_LENGTH(x) (((u32) x) << 3)
+#define TO_DW0_MAXPACKET(x) (((u32) x) << 18)
+#define TO_DW0_MULTI(x) (((u32) x) << 29)
+#define TO_DW0_ENDPOINT(x) (((u32) x) << 31)
+
+/* DW1 */
+#define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3)
+#define TO_DW1_PID_TOKEN(x) (((u32) x) << 10)
+#define DW1_TRANS_BULK ((u32) 2 << 12)
+#define DW1_TRANS_INT ((u32) 3 << 12)
+#define DW1_TRANS_SPLIT ((u32) 1 << 14)
+#define DW1_SE_USB_LOSPEED ((u32) 2 << 16)
+#define TO_DW1_PORT_NUM(x) (((u32) x) << 18)
+#define TO_DW1_HUB_NUM(x) (((u32) x) << 25)
+/* DW2 */
+#define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8)
+#define TO_DW2_RL(x) ((x) << 25)
+#define FROM_DW2_RL(x) (((x) >> 25) & 0xf)
+/* DW3 */
+#define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff)
+#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff)
+#define TO_DW3_NAKCOUNT(x) ((x) << 19)
+#define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf)
+#define TO_DW3_CERR(x) ((x) << 23)
+#define FROM_DW3_CERR(x) (((x) >> 23) & 0x3)
+#define TO_DW3_DATA_TOGGLE(x) ((x) << 25)
+#define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1)
+#define TO_DW3_PING(x) ((x) << 26)
+#define FROM_DW3_PING(x) (((x) >> 26) & 0x1)
+#define DW3_ERROR_BIT (1 << 28)
+#define DW3_BABBLE_BIT (1 << 29)
+#define DW3_HALT_BIT (1 << 30)
+#define DW3_ACTIVE_BIT (1 << 31)
+#define FROM_DW3_ACTIVE(x) (((x) >> 31) & 0x01)
+
+#define INT_UNDERRUN (1 << 2)
+#define INT_BABBLE (1 << 1)
+#define INT_EXACT (1 << 0)
+
+#define SETUP_PID (2)
+#define IN_PID (1)
+#define OUT_PID (0)
+
+/* FIXME!: Does this apply to isp1763? ST-Ericsson believes no */
+/* Set these to HW defaults of ZERO? */
+/* Errata 1 */
+#define RL_COUNTER (0) /* isp1760 (0) */
+#define NAK_COUNTER (0) /* isp1760 (0) */
+#define ERR_COUNTER (0) /* isp1760 (2) */
+
+#endif /* _ISP1763_HCD_H_ */
diff --git a/drivers/usb/host/isp1763-if.c b/drivers/usb/host/isp1763-if.c
new file mode 100644
index 0000000..c07dcdb
--- /dev/null
+++ b/drivers/usb/host/isp1763-if.c
@@ -0,0 +1,523 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published
+ * by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ *
+ * Description:
+ *
+ * Glue code for the ISP1763 driver and bus
+ * Currently there is support for:
+ * - OpenFirmware
+ * - PCI (not-tested; as-is port from isp1760)
+ * - PDEV (generic platform device centralized driver model)
+ *
+ * Based on isp1760 driver by:
+ * Sebastian Andrzej Siewior <sebastian@xxxxxxxxxxxxx>
+ * Arvid Brodin <arvid.brodin@xxxxxxxx>
+ * and pehci code from ST-Ericsson <wired.support@xxxxxxxxxxxxxx>
+ *
+ */
+#include <linux/usb.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/usb/isp1763.h>
+
+#include <linux/usb/hcd.h>
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+
+#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_gpio.h>
+#endif
+
+#ifdef CONFIG_PCI
+#include <linux/pci.h>
+#endif
+
+#include "isp1763-hcd.h"
+
+#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
+struct isp1763 {
+ struct usb_hcd *hcd;
+ int rst_gpio;
+};
+
+static int of_isp1763_probe(struct platform_device *dev)
+{
+ struct isp1763 *drvdata;
+ struct device_node *dp = dev->dev.of_node;
+ struct resource *res;
+ struct resource memory;
+ int virq;
+ resource_size_t res_len;
+ int ret;
+ const unsigned int *prop;
+ unsigned int devflags = 0;
+ enum of_gpio_flags gpio_flags;
+ /* FIXME: of_property_read_u32() is not available until linux-3.1
+ * u32 bus_width = 0; */
+
+ drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
+ if (!drvdata)
+ return -ENOMEM;
+
+ ret = of_address_to_resource(dp, 0, &memory);
+ if (ret) {
+ pr_warn("of_isp1763: Memory resource not available\n");
+ ret = -ENXIO;
+ goto free_data;
+ }
+
+ res_len = resource_size(&memory);
+
+ res = request_mem_region(memory.start, res_len, dev_name(&dev->dev));
+ if (!res) {
+ pr_warn("of_isp1763: Cannot reserve the memory resource\n");
+ ret = -EBUSY;
+ goto free_data;
+ }
+
+ virq = irq_of_parse_and_map(dp, 0);
+ if (!virq) {
+ pr_warn("of_isp1763: IRQ resource not available\n");
+ ret = -ENODEV;
+ goto release_reg;
+ }
+
+ /* FIXME:
+ * of_property_read_u32() is not available until linux-3.1
+ *
+ * of_property_read_u32(dp, "bus-width", &bus_width);
+ * if (bus_width == 16)
+ * devflags |= ISP1763_FLAG_BUS_WIDTH_8;
+ */
+ /* Some systems wire up only 8 of the 16 data lines */
+ prop = of_get_property(dp, "bus-width", NULL);
+ if (prop && *prop == 8)
+ devflags |= ISP1763_FLAG_BUS_WIDTH_8;
+
+ if (of_get_property(dp, "port1-otg", NULL) != NULL)
+ devflags |= ISP1763_FLAG_OTG_EN;
+
+ if (of_get_property(dp, "dack-polarity-high", NULL) != NULL)
+ devflags |= ISP1763_FLAG_DACK_POL_HIGH;
+
+ if (of_get_property(dp, "dreq-polarity-high", NULL) != NULL)
+ devflags |= ISP1763_FLAG_DREQ_POL_HIGH;
+
+ if (of_get_property(dp, "intr-polarity-high", NULL) != NULL)
+ devflags |= ISP1763_FLAG_INTR_POL_HIGH;
+
+ if (of_get_property(dp, "intr-edge-trig", NULL) != NULL)
+ devflags |= ISP1763_FLAG_INTR_EDGE_TRIG;
+
+ pr_info("%s: devflags: 0x%X", __func__, devflags);
+
+ drvdata->rst_gpio = of_get_gpio_flags(dp, 0, &gpio_flags);
+ if (gpio_is_valid(drvdata->rst_gpio)) {
+ ret = gpio_request(drvdata->rst_gpio, dev_name(&dev->dev));
+ if (!ret) {
+ if (!(gpio_flags & OF_GPIO_ACTIVE_LOW)) {
+ devflags |= ISP1763_FLAG_RESET_ACTIVE_HIGH;
+ gpio_direction_output(drvdata->rst_gpio, 0);
+ } else {
+ gpio_direction_output(drvdata->rst_gpio, 1);
+ }
+ } else {
+ drvdata->rst_gpio = ret;
+ }
+ }
+
+ drvdata->hcd = isp1763_register(memory.start, res_len, virq,
+ IRQF_SHARED, drvdata->rst_gpio,
+ &dev->dev, dev_name(&dev->dev),
+ devflags);
+ if (IS_ERR(drvdata->hcd)) {
+ ret = PTR_ERR(drvdata->hcd);
+ goto free_gpio;
+ }
+
+ dev_set_drvdata(&dev->dev, drvdata);
+ return ret;
+
+free_gpio:
+ if (gpio_is_valid(drvdata->rst_gpio))
+ gpio_free(drvdata->rst_gpio);
+
+release_reg:
+ release_mem_region(memory.start, res_len);
+free_data:
+ kfree(drvdata);
+ return ret;
+}
+
+static int of_isp1763_remove(struct platform_device *dev)
+{
+ struct isp1763 *drvdata = dev_get_drvdata(&dev->dev);
+
+ dev_set_drvdata(&dev->dev, NULL);
+
+ usb_remove_hcd(drvdata->hcd);
+ iounmap(drvdata->hcd->regs);
+ release_mem_region(drvdata->hcd->rsrc_start, drvdata->hcd->rsrc_len);
+ usb_put_hcd(drvdata->hcd);
+
+ if (gpio_is_valid(drvdata->rst_gpio))
+ gpio_free(drvdata->rst_gpio);
+
+ kfree(drvdata);
+ return 0;
+}
+
+static const struct of_device_id of_isp1763_match[] = {
+ {
+ .compatible = "nxp,usb-isp1763",
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(of, of_isp1763_match);
+
+static struct platform_driver isp1763_of_driver = {
+ .driver = {
+ .name = "nxp-isp1763",
+ .owner = THIS_MODULE,
+ .of_match_table = of_isp1763_match,
+ },
+ .probe = of_isp1763_probe,
+ .remove = of_isp1763_remove,
+};
+#endif /* CONFIG_OF */
+
+#ifdef CONFIG_PCI
+static int isp1763_pci_probe(struct pci_dev *dev,
+ const struct pci_device_id *id)
+{
+ u8 latency, limit;
+ __u32 reg_data;
+ int retry_count;
+ struct usb_hcd *hcd;
+ unsigned int devflags = 0;
+ int ret_status = 0;
+
+ resource_size_t pci_mem_phy0;
+ resource_size_t memlength;
+
+ u8 __iomem *chip_addr;
+ u8 __iomem *iobase;
+ resource_size_t nxp_pci_io_base;
+ resource_size_t iolength;
+
+ if (usb_disabled())
+ return -ENODEV;
+
+ if (pci_enable_device(dev) < 0)
+ return -ENODEV;
+
+ if (!dev->irq)
+ return -ENODEV;
+
+ /* Grab the PLX PCI mem maped port start address we need */
+ nxp_pci_io_base = pci_resource_start(dev, 0);
+ iolength = pci_resource_len(dev, 0);
+
+ if (!request_mem_region(nxp_pci_io_base, iolength, "ISP1763 IO MEM")) {
+ pr_err("request region #1\n");
+ return -EBUSY;
+ }
+
+ iobase = ioremap_nocache(nxp_pci_io_base, iolength);
+ if (!iobase) {
+ pr_err("ioremap #1\n");
+ ret_status = -ENOMEM;
+ goto cleanup1;
+ }
+ /* Grab the PLX PCI shared memory of the ISP 1763 we need */
+ pci_mem_phy0 = pci_resource_start(dev, 3);
+ memlength = pci_resource_len(dev, 3);
+ if (memlength < 0xffff) {
+ pr_err("memory length for this resource is wrong\n");
+ ret_status = -ENOMEM;
+ goto cleanup2;
+ }
+
+ if (!request_mem_region(pci_mem_phy0, memlength, "ISP-PCI")) {
+ pr_err("host controller already in use\n");
+ ret_status = -EBUSY;
+ goto cleanup2;
+ }
+
+ /* map available memory */
+ chip_addr = ioremap_nocache(pci_mem_phy0, memlength);
+ if (!chip_addr) {
+ pr_err("Error ioremap failed\n");
+ ret_status = -ENOMEM;
+ goto cleanup3;
+ }
+
+ /* bad pci latencies can contribute to overruns */
+ pci_read_config_byte(dev, PCI_LATENCY_TIMER, &latency);
+ if (latency) {
+ pci_read_config_byte(dev, PCI_MAX_LAT, &limit);
+ if (limit && limit < latency)
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, limit);
+ }
+
+ /* Try to check whether we can access Scratch Register of
+ * Host Controller or not. The initial PCI access is retried until
+ * local init for the PCI bridge is completed
+ */
+ retry_count = 20;
+ reg_data = 0;
+ while ((reg_data != 0xFACE) && retry_count) {
+ /*by default host is in 16bit mode, so
+ * io operations at this stage must be 16 bit
+ * */
+ writel(0xface, chip_addr + HC_SCRATCH_REG);
+ udelay(100);
+ reg_data = readl(chip_addr + HC_SCRATCH_REG) & 0x0000ffff;
+ retry_count--;
+ }
+
+ iounmap(chip_addr);
+
+ /* Host Controller presence is detected by writing to scratch register
+ * and reading back and checking the contents are same or not
+ */
+ if (reg_data != 0xFACE) {
+ dev_err(&dev->dev, "scratch register mismatch %x\n", reg_data);
+ ret_status = -ENOMEM;
+ goto cleanup3;
+ }
+
+ pci_set_master(dev);
+
+ /* configure PLX PCI chip to pass interrupts */
+#define PLX_INT_CSR_REG 0x68
+ reg_data = readl(iobase + PLX_INT_CSR_REG);
+ reg_data |= 0x900;
+ writel(reg_data, iobase + PLX_INT_CSR_REG);
+
+ dev->dev.dma_mask = NULL;
+ hcd = isp1763_register(pci_mem_phy0, memlength, dev->irq,
+ IRQF_SHARED, -ENOENT, &dev->dev, dev_name(&dev->dev),
+ devflags);
+ if (IS_ERR(hcd)) {
+ ret_status = -ENODEV;
+ goto cleanup3;
+ }
+
+ /* done with PLX IO access */
+ iounmap(iobase);
+ release_mem_region(nxp_pci_io_base, iolength);
+
+ pci_set_drvdata(dev, hcd);
+ return 0;
+
+cleanup3:
+ release_mem_region(pci_mem_phy0, memlength);
+cleanup2:
+ iounmap(iobase);
+cleanup1:
+ release_mem_region(nxp_pci_io_base, iolength);
+ return ret_status;
+}
+
+static void isp1763_pci_remove(struct pci_dev *dev)
+{
+ struct usb_hcd *hcd;
+
+ hcd = pci_get_drvdata(dev);
+
+ usb_remove_hcd(hcd);
+ iounmap(hcd->regs);
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ usb_put_hcd(hcd);
+
+ pci_disable_device(dev);
+}
+
+static void isp1763_pci_shutdown(struct pci_dev *dev)
+{
+ pr_err("ips1763_pci_shutdown\n");
+}
+
+static const struct pci_device_id isp1763_plx[] = {
+ {
+ .class = PCI_CLASS_BRIDGE_OTHER << 8,
+ .class_mask = ~0,
+ .vendor = PCI_VENDOR_ID_PLX,
+ .device = 0x5406,
+ .subvendor = PCI_VENDOR_ID_PLX,
+ .subdevice = 0x9054,
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(pci, isp1763_plx);
+
+static struct pci_driver isp1763_pci_driver = {
+ .name = "isp1763",
+ .id_table = isp1763_plx,
+ .probe = isp1763_pci_probe,
+ .remove = isp1763_pci_remove,
+ .shutdown = isp1763_pci_shutdown,
+};
+#endif /* CONFIG_PCI */
+
+static int isp1763_plat_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+ struct usb_hcd *hcd;
+ struct resource *mem_res;
+ struct resource *irq_res;
+ resource_size_t mem_size;
+ struct isp1763_platform_data *priv = pdev->dev.platform_data;
+ unsigned int devflags = 0;
+ unsigned long irqflags = IRQF_SHARED;
+
+ mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mem_res) {
+ pr_warn("%s: Memory resource not available\n", __func__);
+ ret = -ENODEV;
+ goto out;
+ }
+ mem_size = resource_size(mem_res);
+ if (!request_mem_region(mem_res->start, mem_size, "isp1763")) {
+ pr_warn("%s: Cannot reserve the memory resource\n", __func__);
+ ret = -EBUSY;
+ goto out;
+ }
+
+ irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!irq_res) {
+ pr_warn("%s: IRQ resource not available\n", __func__);
+ return -ENODEV;
+ }
+ irqflags |= irq_res->flags & IRQF_TRIGGER_MASK;
+
+ if (priv) {
+ if (priv->bus_width_8)
+ devflags |= ISP1763_FLAG_BUS_WIDTH_8;
+ if (priv->port1_otg)
+ devflags |= ISP1763_FLAG_OTG_EN;
+ if (priv->dack_polarity_high)
+ devflags |= ISP1763_FLAG_DACK_POL_HIGH;
+ if (priv->dreq_polarity_high)
+ devflags |= ISP1763_FLAG_DREQ_POL_HIGH;
+ if (priv->intr_polarity_high)
+ devflags |= ISP1763_FLAG_INTR_POL_HIGH;
+ if (priv->intr_edge_trigger)
+ devflags |= ISP1763_FLAG_INTR_EDGE_TRIG;
+ }
+
+ hcd = isp1763_register(mem_res->start, mem_size, irq_res->start,
+ irqflags, -ENOENT,
+ &pdev->dev, dev_name(&pdev->dev), devflags);
+ if (IS_ERR(hcd)) {
+ pr_warn("%s: Failed to register the HCD device\n", __func__);
+ /* Mark the hcd pointer as bad for platform_get_drvdata() */
+ platform_set_drvdata(pdev, NULL);
+
+ ret = -ENODEV;
+ goto cleanup;
+ }
+
+ /* Needed to reference back for platform_get_drvdata cleanup */
+ /* platform_set_drvdata() is a wrapper for dev_set_drvdata() */
+ platform_set_drvdata(pdev, hcd);
+
+ pr_info("%s: isp1763 USB device initialised\n", __func__);
+ return ret;
+
+cleanup:
+ release_mem_region(mem_res->start, mem_size);
+out:
+ return ret;
+}
+
+static int isp1763_plat_remove(struct platform_device *pdev)
+{
+ /* Get a handle to the hcd and then clear it from pdev */
+ /* platform_get_drvdata() is a wrapper for dev_get_drvdata() */
+ struct usb_hcd *hcd = NULL;
+
+ hcd = platform_get_drvdata(pdev);
+ platform_set_drvdata(pdev, NULL);
+
+ /* Remove the hcd */
+ usb_remove_hcd(hcd); /* calls free_irq() */
+ iounmap(hcd->regs);
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ usb_put_hcd(hcd);
+ return 0;
+}
+
+static struct platform_driver isp1763_plat_driver = {
+ .probe = isp1763_plat_probe,
+ .remove = isp1763_plat_remove,
+ .driver = {
+ .name = "isp1763",
+ },
+};
+
+static int __init isp1763_init(void)
+{
+ int ret, any_ret = -ENODEV;
+
+ init_kmem_once();
+
+ ret = platform_driver_register(&isp1763_plat_driver);
+ if (!ret)
+ any_ret = 0;
+#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
+ ret = platform_driver_register(&isp1763_of_driver);
+ if (!ret)
+ any_ret = 0;
+#endif
+#ifdef CONFIG_PCI
+ ret = pci_register_driver(&isp1763_pci_driver);
+ if (!ret)
+ any_ret = 0;
+#endif
+
+ if (any_ret)
+ deinit_kmem_cache();
+
+ return any_ret;
+}
+module_init(isp1763_init);
+
+static void __exit isp1763_exit(void)
+{
+ platform_driver_unregister(&isp1763_plat_driver);
+
+#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
+ platform_driver_unregister(&isp1763_of_driver);
+#endif
+#ifdef CONFIG_PCI
+ pci_unregister_driver(&isp1763_pci_driver);
+#endif
+
+ deinit_kmem_cache();
+}
+module_exit(isp1763_exit);
+
+MODULE_DESCRIPTION("ISP1763 USB host-controller from ST-Ericsson");
+MODULE_AUTHOR("Richard Retanubun <richardretanubun@xxxxxxxxxxxxx>");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/usb/isp1763.h b/include/linux/usb/isp1763.h
new file mode 100644
index 0000000..662077f
--- /dev/null
+++ b/include/linux/usb/isp1763.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) RuggedCom 2010
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published
+ * by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA 02110-1301, USA.
+ *
+ * Description:
+ * Adapted from isp1760.h
+ *
+ * board initialization should put one of these into dev->platform_data
+ * and place the isp1763 onto platform_bus named "isp1763-hcd".
+ */
+
+#ifndef __LINUX_USB_ISP1763_H
+#define __LINUX_USB_ISP1763_H
+
+struct isp1763_platform_data {
+ unsigned bus_width_8:1; /* 8/16-bit data bus width */
+ unsigned port1_otg:1; /* Port 1 supports OTG */
+ unsigned dack_polarity_high:1; /* DACK active high */
+ unsigned dreq_polarity_high:1; /* DREQ active high */
+ unsigned intr_polarity_high:1; /* INTR active high */
+ unsigned intr_edge_trigger:1; /* INTR edge trigger */
+};
+
+#endif /* __LINUX_USB_ISP1763_H */
--
1.7.10.4
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