On 03/14/2013 09:34 AM, Peter Chen wrote: > Hi Alex and all, > > Currently, we have two problems to block chipidea driver coming > development. > > As there are so many chipidea versions, we impossible to collect > all to make a decision, it is better to cover most of the cases, > and using device tree (or platform data) to cover exceptions > if they exist. > > 1. USB Mode Problem > How can we decide USB mode (gadget, host and otg) at driver, and > how to read OTGSC register? Below is my pinion. > > - We get gadget or host support from CAP_DCCPARAMS(DCCPARAMS_DC or DCCPARAMS_HC), IIRC This is broken on mx25. The host only port gets into an error state if you read this register. :( > If both DCCPARAMS_DC and DCCPARAMS_HC are 1, then the mode is "otg". > If DCCPARAMS_DC = 1 and DCCPARAMS_HC = 0, the mode is "gadget". > If DCCPARAMS_DC = 0 and DCCPARAMS_HC = 1, the mode is "host". > If DCCPARAMS_DC = 0 and DCCPARAMS_HC = 0, prompt an error > and try to get it from DT. > > - Override the value using DT, please do not consider too much between > dule_role and otg. We just consider all controllers which supports host > and gadget at the same time as otg device. The exception may not be existed > or be too long to use. > - For how to read OTGSC register, we need another flag to indicate > it is otg capable (DCCPARAMS_DC = 1 and DCCPARAMS_HC = 1), if it is > otg capable, read OTGSC is allowed. Here, OTG capable device can work > as gadget only mode. There is a core on mips which doesn't support otg. From my point of view, support for dual_role should be a separate patch, ideally by Svetoslav (Cc'ed) who has this hardware, after we've cleaned up all dr-mode related stuff. > 2. Chipidea Core Driver DT Support > I agree we move some core things, like vbus, operation_mode, phy to core > driver using DT. But for clock, it is better still exist at glue > layer, clock is input for chipidea core, chipidea core doesn't need > to know its clock from IC point. Like clock, the wakeup setting, low > power sequence are platform specific, they are designed by individual > companies. The IP core has (IIRC) 3 clock inputs (AHB, PER, IPG), depending on Vendor and SoC Version the driver has to cope with 0-3 of these clocks. Iff we put the clock handling into the core driver, there have to be all three clocks (and sophisticated error handling to handle non existing clocks). > Let me know your opinion about these two problems and your plan for them. > Thanks. Marc -- Pengutronix e.K. | Marc Kleine-Budde | Industrial Linux Solutions | Phone: +49-231-2826-924 | Vertretung West/Dortmund | Fax: +49-5121-206917-5555 | Amtsgericht Hildesheim, HRA 2686 | http://www.pengutronix.de |
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