simulate Isochronous IN transfers

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Hello,

I have been successful at testing code and getting data on my virtual Fedrora 17
machine, using libusb on the Host side and dummy_hcd and g_zero gadget driver on
the device side.  The source/sink and loopback testing works fine...

However, as I am waiting for hardware to be developed and tested I would like to
keep advancing my simulations to include isochronous transfers IN to the host
from the simulated device.

It appears that the dummy_hcd module does not support the isochronous transfers.

Can anyone recommend a way to simulated the device end for these types of
transfers, in a manner similar to what is being done with dummy_hcd,g_zero and
the f_sourcesink module.

thanks,

dc

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