Re: Need help for hardware bug in Intel's EHCI implementation

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On Fri, 7 Dec 2012, Sarah Sharp wrote:

> On Fri, Dec 07, 2012 at 05:51:55PM -0500, Alan Stern wrote:
> > Sarah:
> > 
> > I just tracked down a tricky problem, which appears to be caused by a
> > genuine hardware bug.  It's hard to believe this has escaped everyone's
> > notice for so many years -- maybe my results are wrong.  But as far as
> > I can tell, they aren't.
> > 
> > Anyway, I don't know what to do about it.  Can you forward this message 
> > to an appropriate person at Intel?
> 
> Sure, I'll try to track the right hardware person down.  I'm afraid they
> might not be able to help, because they may not remember hardware that is
> that old. :-/

For all I know, newer hardware might behave the same way.  It's easy 
enough to test if there's a g-zero gadget at hand, or the equivalent (a 
high-speed device with a bulk-out endpoint that acts as a sink, 
accepting all packets).

After some thought, I now have an idea for a workaround: add a 1-ms
delay whenever a QH is unlinked because of a halt or a dequeue.  
(Presumably 1 ms is enough time.)  Since those are exceptional events,
the extra overhead would be acceptable.

Still, I would like to check with somebody in a position to confirm or 
refute this bug.

Alan Stern

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