On Thu, Nov 15, 2012 at 04:34:13PM +0200, Roger Quadros wrote:
> Instead of enabling the USB PHY clock in the board file we
> provide the PHY clock details to the driver via board platform
> data so that driver code can manage the clock.
>
> Signed-off-by: Roger Quadros <rogerq@xxxxxx>
this patch is ok-ish. But clock should be managed by PHY driver instead.
> ---
> arch/arm/mach-omap2/board-omap4panda.c | 14 +++-----------
> 1 files changed, 3 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
> index bfcd397..b942abe 100644
> --- a/arch/arm/mach-omap2/board-omap4panda.c
> +++ b/arch/arm/mach-omap2/board-omap4panda.c
> @@ -151,7 +151,9 @@ static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
> .phy_reset = false,
> .reset_gpio_port[0] = -EINVAL,
> .reset_gpio_port[1] = -EINVAL,
> - .reset_gpio_port[2] = -EINVAL
> + .reset_gpio_port[2] = -EINVAL,
> + .clk[0] = "auxclk3_ck", /* FREF_CLK3 provides 19.2 MHz clock to PHY */
> + .clkrate[0] = 19200000,
> };
>
> static struct gpio panda_ehci_gpios[] __initdata = {
> @@ -162,16 +164,6 @@ static struct gpio panda_ehci_gpios[] __initdata = {
> static void __init omap4_ehci_init(void)
> {
> int ret;
> - struct clk *phy_ref_clk;
> -
> - /* FREF_CLK3 provides the 19.2 MHz reference clock to the PHY */
> - phy_ref_clk = clk_get(NULL, "auxclk3_ck");
> - if (IS_ERR(phy_ref_clk)) {
> - pr_err("Cannot request auxclk3\n");
> - return;
> - }
> - clk_set_rate(phy_ref_clk, 19200000);
> - clk_prepare_enable(phy_ref_clk);
>
> /* disable the power to the usb hub prior to init and reset phy+hub */
> ret = gpio_request_array(panda_ehci_gpios,
> --
> 1.7.4.1
>
--
balbi
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