ISSUE: When a bit of EHCI status register (USBSTS) is set
as 1, if the corresponded bit of EHCI interrupt enable
register(USBINTR) is set as 1, an interrupt occurs.
After that, even if the bit of USBINTR is set as 0, the
interrupt continues occurring.
Workaround: Clear the bit 3 of USBSTS before enabling the
interrupt, at resume process.
This patch is for
Intel EG20T PCH
LAPIS Semiconductor ML7213 IOH
LAPIS Semiconductor ML7223 IOH
LAPIS Semiconductor ML7831 IOH
Signed-off-by: Tomoya MORINAGA <tomoya.rohm@xxxxxxxxx>
---
drivers/usb/host/ehci-pci.c | 24 ++++++++++++++++++++++++
1 files changed, 24 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index 01bb7241d..30f3ad6 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -419,6 +419,30 @@ static int ehci_pci_resume(struct usb_hcd *hcd, bool hibernated)
ehci_prepare_ports_for_controller_resume(ehci);
if (!hcd->self.root_hub->do_remote_wakeup)
mask &= ~STS_PCD;
+
+ if ((pdev->vendor == PCI_VENDOR_ID_INTEL &&
+ pdev->device == 0x8807) ||
+ (pdev->vendor == PCI_VENDOR_ID_INTEL &&
+ pdev->device == 0x880F) ||
+ (pdev->vendor == 0x10DB &&
+ pdev->device == 0x801C) || /* ML7213 */
+ (pdev->vendor == 0x10DB &&
+ pdev->device == 0x8007) || /* ML7223 */
+ (pdev->vendor == 0x10DB &&
+ pdev->device == 0x8807)) { /* ML7831 */
+ /* ISSUE: When a bit of EHCI status register (USBSTS) is set
+ * as 1, if the corresponded bit of EHCI interrupt enable
+ * register(USBINTR) is set as 1, an interrupt occurs.
+ * After that, even if the bit of USBINTR is set as 0, the
+ * interrupt continues occurring.
+ * Workaround: Clear the bit 3 of USBSTS before enabling the
+ * interrupt, at resume process.
+ */
+ ehci_writel(ehci, STS_FLR, &ehci->regs->status);
+ ehci_dbg(ehci, "Workaround: %s: Clear STS_FLR\n",
+ __func__);
+ }
+
ehci_writel(ehci, mask, &ehci->regs->intr_enable);
ehci_readl(ehci, &ehci->regs->intr_enable);
return 0;
--
1.7.7.6
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