ISSUE: When a bit of EHCI status register (USBSTS) is set
as 1, if the corresponded bit of EHCI interrupt enable
register(USBINTR) is set as 1, an interrupt occurs.
After that, even if the bit of USBINTR is set as 0, the
interrupt continues occurring.
Workaround: Clear the bit 3 of USBSTS before enabling the
interrupt, at resume process.
This patch is for
Intel EG20T PCH
LAPIS Semiconductor ML7213 IOH
LAPIS Semiconductor ML7223 IOH
LAPIS Semiconductor ML7831 IOH
Signed-off-by: Tomoya MORINAGA <tomoya.rohm@xxxxxxxxx>
---
drivers/usb/host/ehci-hub.c | 18 ++++++++++++++++++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
index 256fbd4..7ddb62e 100644
--- a/drivers/usb/host/ehci-hub.c
+++ b/drivers/usb/host/ehci-hub.c
@@ -342,6 +342,7 @@ static int ehci_bus_resume (struct usb_hcd *hcd)
u32 power_okay;
int i;
unsigned long resume_needed = 0;
+ struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
if (time_before (jiffies, ehci->next_statechange))
msleep(5);
@@ -451,6 +452,23 @@ static int ehci_bus_resume (struct usb_hcd *hcd)
ehci->next_statechange = jiffies + msecs_to_jiffies(5);
+ if ((pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x8807) ||
+ (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x880F) ||
+ (pdev->vendor == 0x10DB && pdev->device == 0x801C) || /* ML7213 */
+ (pdev->vendor == 0x10DB && pdev->device == 0x8007) || /* ML7223 */
+ (pdev->vendor == 0x10DB && pdev->device == 0x8807)) { /* ML7831 */
+ /* ISSUE: When a bit of EHCI status register (USBSTS) is set
+ * as 1, if the corresponded bit of EHCI interrupt enable
+ * register(USBINTR) is set as 1, an interrupt occurs.
+ * After that, even if the bit of USBINTR is set as 0, the
+ * interrupt continues occurring.
+ * Workaround: Clear the bit 3 of USBSTS before enabling the
+ * interrupt, at resume process.
+ */
+ ehci_writel(ehci, STS_FLR, &ehci->regs->status);
+ ehci_dbg(ehci, "Workaround: %s: Clear STS_FLR\n", __func__);
+ }
+
/* Now we can safely re-enable irqs */
ehci_writel(ehci, INTR_MASK, &ehci->regs->intr_enable);
--
1.7.7.6
--
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