Are you sure this patch really preserves bit 3? I think that the code
in pci-quirks.c that uses XHCI_LEGACY_DISABLE_SMI is just bogus:
/* Disable any BIOS SMIs */
writel(XHCI_LEGACY_DISABLE_SMI,
base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
Note that it never *reads* the value of the register, it just writes the
mask to the register. So it's writing all ones to those bits that are
supposed to be preserved, including bit 3.
The code should be:
val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
writel(val & XHCI_LEGACY_DISABLE_SMI,
base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
Please update your patch. Also, you might want to take a look at the
pci-quirks code to see if there's any other preserved bits that I'm
stomping on.
Sarah Sharp
On Thu, Mar 22, 2012 at 03:11:41PM +0800, Alex He wrote:
> Extend reserved bit [1:2] to [1:3] according USBLEGCTLSTS register
> define in xHCI spec.
>
> Signed-off-by: Alex He <alex.he@xxxxxxx>
> ---
> drivers/usb/host/xhci-ext-caps.h | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/host/xhci-ext-caps.h b/drivers/usb/host/xhci-ext-caps.h
> index c7f3312..b9c9ffb 100644
> --- a/drivers/usb/host/xhci-ext-caps.h
> +++ b/drivers/usb/host/xhci-ext-caps.h
> @@ -62,8 +62,8 @@
> /* USB Legacy Support Control and Status Register - section 7.1.2 */
> /* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
> #define XHCI_LEGACY_CONTROL_OFFSET (0x04)
> -/* bits 1:2, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
> -#define XHCI_LEGACY_DISABLE_SMI ((0x3 << 1) + (0xff << 5) + (0x7 << 17))
> +/* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
> +#define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17))
>
> /* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
> #define XHCI_L1C (1 << 16)
> --
> 1.7.1
>
>
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