On Wed, Feb 15, 2012 at 02:24:42PM +0800, Peter Chen wrote: > According to USB2.0 spec 8.5.3.3, for Control Read transfer, > it should prime status stage as soon as prime data stage, as > the data complete irq may never occur if the situation of ch8.5.3.3 > happens. > > Delete below code at fsl_ep_queue: > /* Update ep0 state */ > if ((ep_index(ep) == 0)) > udc->ep0_state = DATA_STATE_XMIT; > the udc->ep0_state will be updated again after udc->driver->setup > finishes. > > It is tested at i.mx51 bbg board with g_mass_storage, g_ether, g_serial. please re-work your subject and commitlog a little bit. You need to make it clearer what the problem really is. If you simply refer to section 8.5.3.3 of USB2.0 specification, you will be expecting people to go look for USB2.0 specification to figure out what your patch is trying to fix and if it really makes sense. -- balbi
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