Hi, On Mon, Jan 02, 2012 at 08:29:07AM -0800, Ido Shayevitz wrote: > > On Sun, Jan 01, 2012 at 12:44:59PM -0800, idos@xxxxxxxxxxxxxx wrote: > >> I wonder if there is a work being done for OTG2.0 driver support over > >> the Synopsys dwc3 core? If so, which git/branch contain this driver? > > > > Sure there is :-) But in order to get there we must first stabilize the > > host side and that we haven't achieved yet. > > > > Still, the newest code for this driver lies in my master branch. Just > > grab a hold of that one. > > > > -- > > balbi > > > > Thanks Felipe, > > I see that in the dwc3_probe also xhci host device is constructed with the > same irq and address base(of dwc3 core), but I couldn't see any true, but we still have some pending patches on the xHCI stack to get the whole thing working out of the box with mainline kernel. Unfortunately we won't have that on 3.3 merge window. But on 3.4 it's likely that it will be there. > configuration done to the OTG registers nor a read of OSTS.ConIDSts for > determining A or B device. That OTG address space isn't implemented by all cores. So you need to find a way to implement that address space without breaking other users. The best way would be to check if GHWPARAMS6[10] is 1. In that case you will have SRP enabled, which means DWC_USB3_EN_OTG is also enabled. If that's true, then you can access the OTG address space. > I guess that the otg driver should implement the programming model > starting from figure 12-4 in the dwc3 controller spec. Indeed. See that you _must_ be sure that GHWPARAMS6 says you support OTG. Otherwise this will not work for everybody. > If this implementation exists, can you give me a pointer, if not, what > are the plans? We _do_ have plans, but not before mid-2012. Patches are welcome of course. -- balbi
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