Hi,
On Mon, Sep 26, 2011 at 05:42:39PM +0900, Yoshihiro Shimoda wrote:
> R8A66597 has the pin of WR0 and WR1. So, if one write-pin of CPU
> connects to the pins, we have to change the setting of FIFOSEL
> register in the controller. If we don't change the setting,
> the controller cannot send the data of odd length.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> ---
> drivers/usb/gadget/r8a66597-udc.c | 4 +-
> drivers/usb/gadget/r8a66597-udc.h | 38 ++++++++++++++++++++----------------
> 2 files changed, 23 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/usb/gadget/r8a66597-udc.c b/drivers/usb/gadget/r8a66597-udc.c
> index 50991e5..cd2cd16 100644
> --- a/drivers/usb/gadget/r8a66597-udc.c
> +++ b/drivers/usb/gadget/r8a66597-udc.c
> @@ -733,7 +733,7 @@ static void irq_ep0_write(struct r8a66597_ep *ep, struct r8a66597_request *req)
> /* write fifo */
> if (req->req.buf) {
> if (size > 0)
> - r8a66597_write_fifo(r8a66597, ep->fifoaddr, buf, size);
> + r8a66597_write_fifo(r8a66597, ep, buf, size);
the patch looks fine, but changing the prototype of this function
doesn't seem to be part of this patch. So I think you should first fix
that function's prototype, than apply the rest of the fix to WR0 and WR1
as another patch.
--
balbi
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