Hi Paul, On Fri, Sep 23, 2011 at 7:31 AM, Paul Walmsley <paul@xxxxxxxxx> wrote: > The idea of the main_clk was not intended to be PRCM or OCP or even > OMAP-specific. It's just intended to represent a clock that is used to > drive the register logic inside the IP block. Therefore it must be > enabled before any register access may occur. Even if clock gating is > handled by some higher-level interface (e.g., at the IP block level), the > main_clk has a rate, so it also implies an upper limit on how quickly > register operations can occur. I suppose that all of the IP block's > clocks could be "optional clocks," but we know that every IP block with > registers requires at least one clock to work, and that should be the > main_clk. I am a bit confused about you comment on "main_clk". >From hwmod related source code, main_clk is the function clock of one module(hwmod), such as: on omap4, for uart3, main_clk is uart3_fck. But from[1] and [2] of omap4 PRM, we can find that interface clock is required to provide register access instead of function clock. This is a bit conflictive with what you description, so could you give a further comments about main_clk, function clock and interface clock? [1], 23.3.4.2 Clock Configuration Each UART uses a 48-MHz functional clock for its logic and to generate external interface signals. Each UART uses an interface clock for register accesses. [2], 3.1.1.1.1 Module Interface and Functional Clocks The interface clocks have the following characteristics: • They ensure proper communication between any module/subsystem and the interconnect. • In most cases, they supply the system interconnect interface and registers of the module. thanks, -- Ming Lei -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
