Hello Ming Lei, Thank you for your quick and good information. I understood. Thank you Regards Takasugi ********************************************* Texas Instruments Japan Sales and Marketing Yokohama office Takasugi Hirokazu <takasugi@xxxxxx> TEL:03-4331-7124 FAX:045-453-9326 ********************************************* -----Original Message----- From: Ming Lei [mailto:tom.leiming@xxxxxxxxx] Sent: Tuesday, September 20, 2011 9:53 AM To: Takasugi, Hirokazu Cc: Alan Stern; linux-usb@xxxxxxxxxxxxxxx Subject: Re: DM3725 EHCI HOST controller descriptor update timing On Tue, Sep 20, 2011 at 8:13 AM, Takasugi, Hirokazu <takasugi@xxxxxx> >>> 2. Is there the status to confirm in descriptor before updating a Descriptor elsewhere? >> I don't understand this question. Please give more details about what you want to know. > I want to know that the timing of data transfer buffer (Buffer Pointer (Page x)) to another region. > After generated Completion interrupt, can the buffer data move another region by CPU or DMA soon? > (Does the CPU need to know all received data is in DDR region another > way? ) The interrupt is triggered after IOC bit of qtd->hw_token is set. When IOC is set, it means the transfer represented by qtd has finished, eg. EHCI controler has completed the DMA read from memory or DMA write to memory. thanks, -- Ming Lei -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
