DWC OTG / DMA Device/ fails during Get Device Descriptor IN stage if Cable is already connected during kernel boot

[Pratyush Anand <pratyush.anand@xxxxxxxxx>]

Hi All,

I am facing one issue with dwc otg. If anyone has seen similar issue ,
then please let me know.

I have configured DWC OTG as device only.
Have selected DMA mode transfer.
Cable is already connected between OTG and host during kernel booting.

SW receives RESET and ENUMDONE interrupt correctly.
It also receives setup token for first Control command i.e. Get Device
Descriptor.
SW analyses this command and prepares a 18 bytes data to be
transferred by DMA against IN token.
SW programs DIEPDMA and DIEPCTL properly for transfer of this 18 bytes.
But, they are never seen on the bus (Analyser).

		if (c_if->dma_enable)
			dwc_write32(in_regs + DWC_DIEPDMA, ep->dma_addr);
		/* EP enable, IN data in FIFO */
		depctl = DWC_DEPCTL_CLR_NAK_RW(depctl, 1);
		depctl = DWC_DEPCTL_EPENA_RW(depctl, 1);
		dwc_write32(in_regs + DWC_DIEPCTL, depctl);

If I stop the control just after EP Enable (the above code of
dwc_otg_ep0_start_transfer),
I observe that EP is in NAKed state. If I clear this NAK using
debuger, I can see data on the bus.
But surprizingly if I do something like this in the code, I never see
any value increment for temp_count.

                                   temp = dwc_read32(in_regs + DWC_DIEPCTL);
		while (DWC_DEPCTL_NKASTS_RD(temp)) {
			temp_count++;
			pr_info("Error\n");
			dwc_write32(in_regs + DWC_DIEPCTL, depctl);
			temp = dwc_read32(in_regs + DWC_DIEPCTL);
		}

So, it points to the fact that NAK is cleared when SW tries to clear it.
But it is again set by the controller, as data has not been
transferred against received IN token.

Any diagnostic direction would highly be appreciated.

Regards
Pratyush

PS: It works if I connect cable after  kernel booting (ie. OTG has
already been initilized).
It also work, if cable is connected during booting but device is in slave mode.
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