On Fri, Jul 08, 2011 at 02:51:27PM +0900, Yoshihiro Shimoda wrote: > BUSWAIT is a 4-bit-wide value that controls the number of access waits > from the CPU to on-chip USB module. b'0000 inserts 0 wait (2 access > cycles) and b'1111 inserts 15 waits (17 access cycles, hardware > initial value), respectively. > > BUSWAIT value depends on peripheral clock frequency supplied to on-chip > of each CPU, hence should be configurable through platform data. > > Note that this patch assumes that b'0000 (0 wait, 2 access cycles) is > rerely used and considered as invalid. If valid 'buswait' data is not > provided by platform, initial b'1111 (15 waits, 17 access cycles) will > be applied as a safe default. > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx> applied, thanks -- balbi
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