Re: xHCI: Limiting host bInterval for super speed endpoints for Texas Instruments host controllers

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On Thu, Jun 30, 2011 at 09:19:02AM -0500, Schauer, Dwight wrote:
> Hi,
> 
> I've not fully implemented and tested this yet, I just wanted to make sure I was on the right track as far as what to modify in the xhci_hcd module to limit bInterval for super speed endpoints.

It helps if you Cc me. :)  I often end up ignoring the Linux USB mailing
list for days if I'm hacking on some patchset.

> With the TI USB3 host controllers we have found that there is an intermittent enumeration issue with devices whose interrupt EP binterval >7. As a result the xHCI Driver should program binterval = 7 for any device reporting binterval > 7 on the interrupt EP.

>From your patch, it looks like only SuperSpeed interrupt endpoints are
effected, is that true?

> I'm putting the clamping of bInterval in xhci_endpoint_init, but am not sure if this is the correct location.

It's probably the right place for it.  Another way to do it might be to
have the USB core change the stored device descriptors before drivers
have a chance to bind to the device.  Alan might have an opinion on
this.

> #### Start Patch
> diff -wubr host.0/xhci.h host/xhci.h
> --- host.0/xhci.h	2011-06-23 17:06:00.000000000 -0500
> +++ host/xhci.h	2011-06-29 17:27:50.968159616 -0500
> @@ -1287,6 +1287,7 @@
>  #define XHCI_NEC_HOST		(1 << 2)
>  #define XHCI_AMD_PLL_FIX	(1 << 3)
>  #define XHCI_BROKEN_MSI		(1 << 6)
> +#define XHCI_TI_HOST		(1 << 7)
>  	/* There are two roothubs to keep track of bus suspend info for */
>  	struct xhci_bus_state   bus_state[2];
>  	/* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
> diff -wubr host.0/xhci-mem.c host/xhci-mem.c
> --- host.0/xhci-mem.c	2011-06-30 09:01:38.137040233 -0500
> +++ host/xhci-mem.c	2011-06-30 09:02:50.903555788 -0500
> @@ -1195,6 +1195,11 @@
>  	ep_ctx->deq = ep_ring->first_seg->dma | ep_ring->cycle_state;
>  
>  	ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep);
> +
> +	if ((udev->speed == USB_SPEED_SUPER) && (xhci->quirks & XHCI_TI_HOST)) {
> +		ep_ctx->ep_info = clamp_val (ep_ctx->ep_info, 1, 7);
> +	}
> +
>  	ep_ctx->ep_info |= EP_MULT(xhci_get_endpoint_mult(udev, ep));
>  
>  	/* FIXME dig Mult and streams info out of ep companion desc */
> diff -wubr host.0/xhci-pci.c host/xhci-pci.c
> --- host.0/xhci-pci.c	2011-06-23 17:06:00.000000000 -0500
> +++ host/xhci-pci.c	2011-06-29 17:28:47.494708634 -0500
> @@ -124,6 +124,9 @@
>  	if (pdev->vendor == PCI_VENDOR_ID_NEC)
>  		xhci->quirks |= XHCI_NEC_HOST;
>  
> +  if (pdev->vendor == PCI_VENDOR_ID_TI)
> +		xhci->quirks |= XHCI_TI_HOST;
> +
>  	/* AMD PLL quirk */
>  	if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
>  		xhci->quirks |= XHCI_AMD_PLL_FIX;

Do you want to add a specific device ID or PCI revision ID to this
patch?  Your future xHCI host controllers may not have this issue.

Sarah Sharp
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