Re: [PATCH 10/43] USB: musb: blackfin: work around anomaly 05000450

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Hello.

On 16-04-2011 4:05, Greg Kroah-Hartman wrote:

From: Mike Frysinger<vapier@xxxxxxxxxx>

DMA mode 1 data corruption anomaly on Blackfin systems.  This issue is
specific to the Blackfin silicon as the bug appears to be related to the
connection of the musb ip to the bus/dma fabric.

Data corruption when using USB DMA mode 1. (Issue manager 17-01-0105)
DMA mode 1 allows large size transfers to generate a single interrupt
at the end of the entire transfer.  The transfer is split up in packets
of length specified in the Maximum Packet Size field for that endpoint.
If the transfer size is not an integer multiple of the Maximum Packet
Size, a short packet will be present at the end of the transfer.

Under certain conditions this packet may be corrupted in the USB FIFO.

Workaround:
Use DMA mode 1 to transfer (n* Maximum Packet Size) and schedule DMA
mode 0 to transfer the short packet.

As an example if your transfer size is 33168 bytes and Maximum Packet
Size equals 512, schedule [33168 - (33168 mod 512)] in DMA mode 1 and
the remainder (33168 mod 512) in DMA mode 0.

Signed-off-by: Mike Frysinger<vapier@xxxxxxxxxx>
Signed-off-by: Felipe Balbi<balbi@xxxxxx>
[...]

diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 4bd9e21..0e053b5 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -261,6 +261,7 @@ enum musb_g_ep0_state {
   * @try_ilde:	tries to idle the IP
   * @vbus_status: returns vbus status if possible
   * @set_vbus:	forces vbus status
+ * @channel_program: pre check for standard dma channel_program func

   Didn't notice this before: kerneldoc doesn't match the code here.

   */
  struct musb_platform_ops {
  	int	(*init)(struct musb *musb);
@@ -274,6 +275,10 @@ struct musb_platform_ops {

  	int	(*vbus_status)(struct musb *musb);
  	void	(*set_vbus)(struct musb *musb, int on);
+
+	int	(*adjust_channel_params)(struct dma_channel *channel,
+				u16 packet_sz, u8 *mode,
+				dma_addr_t *dma_addr, u32 *len);
  };

  /*

WBR, Sergei
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