Looks fine Andiry, I'll queue this up for 2.6.39 shortly.
Sarah Sharp
On Tue, Apr 19, 2011 at 05:17:39PM +0800, Andiry Xu wrote:
> This patch clears PORT_PLC if xhci_bus_resume() resumes a previous suspended
> port, because if a port transition from U3 to U0 state, it will report a
> port link state change, and software should clear the corresponding PLC bit.
>
> It also uses hcd->speed to check if a port is a USB2 protocol port.
>
> The patch fixes the issue that USB keyboard can not wakeup system from
> hibernation.
>
> Signed-off-by: Andiry Xu <andiry.xu@xxxxxxx>
> ---
> drivers/usb/host/xhci-hub.c | 19 +++++++++++++++++--
> 1 files changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
> index a78f2eb..73f75d2 100644
> --- a/drivers/usb/host/xhci-hub.c
> +++ b/drivers/usb/host/xhci-hub.c
> @@ -777,7 +777,7 @@ int xhci_bus_suspend(struct usb_hcd *hcd)
> if (t1 != t2)
> xhci_writel(xhci, t2, port_array[port_index]);
>
> - if (DEV_HIGHSPEED(t1)) {
> + if (hcd->speed != HCD_USB3) {
> /* enable remote wake up for USB 2.0 */
> u32 __iomem *addr;
> u32 tmp;
> @@ -866,6 +866,21 @@ int xhci_bus_resume(struct usb_hcd *hcd)
> temp |= PORT_LINK_STROBE | XDEV_U0;
> xhci_writel(xhci, temp, port_array[port_index]);
> }
> + /* wait for the port to enter U0 and report port link
> + * state change.
> + */
> + spin_unlock_irqrestore(&xhci->lock, flags);
> + msleep(20);
> + spin_lock_irqsave(&xhci->lock, flags);
> +
> + /* Clear PLC */
> + temp = xhci_readl(xhci, port_array[port_index]);
> + if (temp & PORT_PLC) {
> + temp = xhci_port_state_to_neutral(temp);
> + temp |= PORT_PLC;
> + xhci_writel(xhci, temp, port_array[port_index]);
> + }
> +
> slot_id = xhci_find_slot_id_by_port(hcd,
> xhci, port_index + 1);
> if (slot_id)
> @@ -873,7 +888,7 @@ int xhci_bus_resume(struct usb_hcd *hcd)
> } else
> xhci_writel(xhci, temp, port_array[port_index]);
>
> - if (DEV_HIGHSPEED(temp)) {
> + if (hcd->speed != HCD_USB3) {
> /* disable remote wake up for USB 2.0 */
> u32 __iomem *addr;
> u32 tmp;
> --
> 1.7.1
>
>
>
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