This patch adds test mode support for Langwell gadget driver.
Signed-off-by: Henry Yuan <hang.yuan@xxxxxxxxx>
Signed-off-by: Andy Luo <yifei.luo@xxxxxxxxx>
---
drivers/usb/gadget/langwell_udc.c | 23 +++++++++++++++++++++++
include/linux/usb/langwell_udc.h | 5 +++++
2 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/drivers/usb/gadget/langwell_udc.c b/drivers/usb/gadget/langwell_udc.c
index b8ec954..7779724 100644
--- a/drivers/usb/gadget/langwell_udc.c
+++ b/drivers/usb/gadget/langwell_udc.c
@@ -2225,6 +2225,7 @@ static void handle_setup_packet(struct langwell_udc *dev,
u16 wValue = le16_to_cpu(setup->wValue);
u16 wIndex = le16_to_cpu(setup->wIndex);
u16 wLength = le16_to_cpu(setup->wLength);
+ u32 portsc1;
dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
@@ -2313,6 +2314,28 @@ static void handle_setup_packet(struct langwell_udc *dev,
dev->dev_status &= ~(1 << wValue);
}
break;
+ case USB_DEVICE_TEST_MODE:
+ dev_dbg(&dev->pdev->dev, "SETUP: TEST MODE\n");
+ if ((wIndex & 0xff) ||
+ (dev->gadget.speed != USB_SPEED_HIGH))
+ ep0_stall(dev);
+
+ switch (wIndex >> 8) {
+ case TEST_J:
+ case TEST_K:
+ case TEST_SE0_NAK:
+ case TEST_PACKET:
+ case TEST_FORCE_EN:
+ if (prime_status_phase(dev, EP_DIR_IN))
+ ep0_stall(dev);
+ portsc1 = readl(&dev->op_regs->portsc1);
+ portsc1 |= (wIndex & 0xf00) << 8;
+ writel(portsc1, &dev->op_regs->portsc1);
+ goto end;
+ default:
+ rc = -EOPNOTSUPP;
+ }
+ break;
default:
rc = -EOPNOTSUPP;
break;
diff --git a/include/linux/usb/langwell_udc.h b/include/linux/usb/langwell_udc.h
index 2d2d1bb..deeaabf 100644
--- a/include/linux/usb/langwell_udc.h
+++ b/include/linux/usb/langwell_udc.h
@@ -178,6 +178,11 @@ struct langwell_op_regs {
#define PORTS_WKDS BIT(21) /* wake on disconnect enable */
#define PORTS_WKCN BIT(20) /* wake on connect enable */
#define PORTS_PTC(p) (((p)>>16)&0xf) /* bits 19:16, port test control */
+#define TEST_J 1
+#define TEST_K 2
+#define TEST_SE0_NAK 3
+#define TEST_PACKET 4
+#define TEST_FORCE_EN 5
#define PORTS_PIC (BIT(15) | BIT(14)) /* port indicator control */
#define PORTS_PO BIT(13) /* port owner */
#define PORTS_PP BIT(12) /* port power */
--
1.7.2.1
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