Hi,
I am trying to use the usb xhci driver on powerpc(P2020RDB) board.
But I experience the same problem "devices are not detected".
It was posted in July on this ML.
Does anyone try to fix the problem?
The part of the log here:
(removed the redundant info from the log.)
xhci_hcd : xHCI Host Controller
drivers/usb/core/inode.c: creating file '002'
xhci_hcd : new USB bus registered, assigned bus number 2
xhci_hcd : xHCI capability registers at f21fc000:
xhci_hcd : CAPLENGTH AND HCIVERSION 0x960020:
xhci_hcd : CAPLENGTH: 0x20
xhci_hcd : HCIVERSION: 0x96
xhci_hcd : HCSPARAMS 1: 0x4000820
xhci_hcd : Max device slots: 32
xhci_hcd : Max interrupters: 8
xhci_hcd : Max ports: 4
xhci_hcd : HCSPARAMS 2: 0x11
xhci_hcd : Isoc scheduling threshold: 1
xhci_hcd : Maximum allowed segments in event ring: 1
xhci_hcd : HCSPARAMS 3 0x0:
xhci_hcd : Worst case U1 device exit latency: 0
xhci_hcd : Worst case U2 device exit latency: 0
xhci_hcd : HCC PARAMS 0x14042cb:
xhci_hcd : HC generates 64 bit addresses
xhci_hcd : FIXME: more HCCPARAMS debugging
xhci_hcd : RTSOFF 0x600:
xhci_hcd : xHCI operational registers at f21fc020:
xhci_hcd : USBCMD 0x0:
xhci_hcd : HC is being stopped
xhci_hcd : HC has finished hard reset
xhci_hcd : Event Interrupts disabled
xhci_hcd : Host System Error Interrupts disabled
xhci_hcd : HC has finished light reset
xhci_hcd : USBSTS 0x11:
xhci_hcd : Event ring is empty
xhci_hcd : No Host System Error
xhci_hcd : HC is halted
xhci_hcd : f21fc420 port status reg = 0x2a1203
xhci_hcd : f21fc424 port power reg = 0x0
xhci_hcd : f21fc428 port link reg = 0x0
xhci_hcd : f21fc42c port reserved reg = 0x0
xhci_hcd : f21fc430 port status reg = 0x2802a0
xhci_hcd : f21fc434 port power reg = 0x0
xhci_hcd : f21fc438 port link reg = 0x0
xhci_hcd : f21fc43c port reserved reg = 0x0
xhci_hcd : f21fc440 port status reg = 0x2a0
xhci_hcd : f21fc444 port power reg = 0x0
xhci_hcd : f21fc448 port link reg = 0x0
xhci_hcd : f21fc44c port reserved reg = 0x0
xhci_hcd : f21fc450 port status reg = 0x2a0
xhci_hcd : f21fc454 port power reg = 0x0
xhci_hcd : f21fc458 port link reg = 0x0
xhci_hcd : f21fc45c port reserved reg = 0x0
xhci_hcd : // Halt the HC
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 32'hf21fc020, 32'h0, 4'hf);
xhci_hcd : Resetting HCD
xhci_hcd : // Reset the HC
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 32'hf21fc020, 32'h2, 4'hf);
xhci_hcd : Wait for controller to be ready for doorbell rings
xhci_hcd : Reset complete
xhci_hcd : Enabling 64-bit DMA addresses.
xhci_hcd : Calling HCD init
xhci_hcd : xhci_init
xhci_hcd : xHCI doesn't need link TRB QUIRK
xhci_hcd : Supported page size register = 0x1
xhci_hcd : Supported page size of 4K
xhci_hcd : HCD page size set to 4K
xhci_hcd : // xHC can handle at most 32 device slots.
xhci_hcd : // Setting Max device slots reg = 0x20.
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 32'hf21fc058, 32'h20, 4'hf);
xhci_hcd : // Device context base array address = 0x21dec000 (DMA), e1dec000 (virt)
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 64'hf21fc050, 64'h21dec000, 4'hf);
xhci_hcd : Allocating ring at cee59600
xhci_hcd : Allocating priv segment structure at efbe2220
xhci_hcd : // Allocating segment at d9838000 (virtual) 0x19838000 (DMA)
xhci_hcd : Linking segment 0x19838000 to segment 0x19838000 (DMA)
xhci_hcd : Wrote link toggle flag to segment efbe2220 (virtual), 0x19838000 (DMA)
xhci_hcd : Allocated command ring at cee59600
xhci_hcd : First segment DMA is 0x19838000
xhci_hcd : // Setting command ring address to 0x20
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 64'hf21fc038, 64'h19838001, 4'hf);
xhci_hcd : // xHC command ring deq ptr low bits + flags = @00000000
xhci_hcd : // xHC command ring deq ptr high bits = @00000000
xhci_hcd : // Doorbell array is located at offset 0x800 from cap regs base addr
xhci_hcd : // xHCI capability registers at f21fc000:
xhci_hcd : // @f21fc000 = 0x960020 (CAPLENGTH AND HCIVERSION)
xhci_hcd : // CAPLENGTH: 0x20
xhci_hcd : // xHCI operational registers at f21fc020:
xhci_hcd : // @f21fc018 = 0x600 RTSOFF
xhci_hcd : // xHCI runtime registers at f21fc600:
xhci_hcd : // @f21fc014 = 0x800 DBOFF
xhci_hcd : // Doorbell array at f21fc800:
xhci_hcd : xHCI runtime registers at f21fc600:
xhci_hcd : f21fc600: Microframe index = 0x0
xhci_hcd : // Allocating event ring
xhci_hcd : Allocating ring at cee59400
xhci_hcd : Allocating priv segment structure at efbe2230
xhci_hcd : // Allocating segment at d9838400 (virtual) 0x19838400 (DMA)
xhci_hcd : Linking segment 0x19838400 to segment 0x19838400 (DMA)
xhci_hcd : TRB math tests passed.
xhci_hcd : // Allocated event ring segment table at 0x1ce92000
xhci_hcd : Set ERST to 0; private num segs = 1, virt addr = dce92000, dma addr = 0x1ce92000
xhci_hcd : // Write ERST size = 1 to ir_set 0 (some bits preserved)
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 32'hf21fc628, 32'h1, 4'hf);
xhci_hcd : // Set ERST entries to point to event ring.
xhci_hcd : // Set ERST base address for ir_set 0 = 0x1ce92000
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 64'hf21fc630, 64'h1ce92000, 4'hf);
xhci_hcd : // Write event ring dequeue pointer, preserving EHB bit
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 64'hf21fc638, 64'h19838400, 4'hf);
xhci_hcd : Wrote ERST address to ir_set 0.
xhci_hcd : Allocating 0 scratchpad buffers
xhci_hcd : Finished xhci_init
xhci_hcd : Called HCD init
xhci_hcd : Got SBRN 48
xhci_hcd : MWI active
xhci_hcd : Finished xhci_pci_reinit
xhci_hcd : irq 16, io mem 0xa0000000
xhci_hcd : xhci_run
irq: irq 0 on host /soc@ffe00000/msi@41600 mapped to virtual irq 18
irq: irq 1 on host /soc@ffe00000/msi@41600 mapped to virtual irq 24
irq: irq 2 on host /soc@ffe00000/msi@41600 mapped to virtual irq 25
xhci_hcd : Setting event ring polling timer
xhci_hcd : Command ring memory map follows:
xhci_hcd : @19838000 00000000 00000000 00000000 00000000
xhci_hcd : @19838010 00000000 00000000 00000000 00000000
xhci_hcd : @19838020 00000000 00000000 00000000 00000000
xhci_hcd : @19838030 00000000 00000000 00000000 00000000
xhci_hcd : @19838040 00000000 00000000 00000000 00000000
xhci_hcd : @19838050 00000000 00000000 00000000 00000000
xhci_hcd : @19838060 00000000 00000000 00000000 00000000
xhci_hcd : @19838070 00000000 00000000 00000000 00000000
xhci_hcd : @19838080 00000000 00000000 00000000 00000000
xhci_hcd : @19838090 00000000 00000000 00000000 00000000
xhci_hcd : @198380a0 00000000 00000000 00000000 00000000
xhci_hcd : @198380b0 00000000 00000000 00000000 00000000
xhci_hcd : @198380c0 00000000 00000000 00000000 00000000
xhci_hcd : @198380d0 00000000 00000000 00000000 00000000
xhci_hcd : @198380e0 00000000 00000000 00000000 00000000
xhci_hcd : @198380f0 00000000 00000000 00000000 00000000
xhci_hcd : @19838100 00000000 00000000 00000000 00000000
xhci_hcd : @19838110 00000000 00000000 00000000 00000000
xhci_hcd : @19838120 00000000 00000000 00000000 00000000
xhci_hcd : @19838130 00000000 00000000 00000000 00000000
xhci_hcd : @19838140 00000000 00000000 00000000 00000000
xhci_hcd : @19838150 00000000 00000000 00000000 00000000
xhci_hcd : @19838160 00000000 00000000 00000000 00000000
xhci_hcd : @19838170 00000000 00000000 00000000 00000000
xhci_hcd : @19838180 00000000 00000000 00000000 00000000
xhci_hcd : @19838190 00000000 00000000 00000000 00000000
xhci_hcd : @198381a0 00000000 00000000 00000000 00000000
xhci_hcd : @198381b0 00000000 00000000 00000000 00000000
xhci_hcd : @198381c0 00000000 00000000 00000000 00000000
xhci_hcd : @198381d0 00000000 00000000 00000000 00000000
xhci_hcd : @198381e0 00000000 00000000 00000000 00000000
xhci_hcd : @198381f0 00000000 00000000 00000000 00000000
xhci_hcd : @19838200 00000000 00000000 00000000 00000000
xhci_hcd : @19838210 00000000 00000000 00000000 00000000
xhci_hcd : @19838220 00000000 00000000 00000000 00000000
xhci_hcd : @19838230 00000000 00000000 00000000 00000000
xhci_hcd : @19838240 00000000 00000000 00000000 00000000
xhci_hcd : @19838250 00000000 00000000 00000000 00000000
xhci_hcd : @19838260 00000000 00000000 00000000 00000000
xhci_hcd : @19838270 00000000 00000000 00000000 00000000
xhci_hcd : @19838280 00000000 00000000 00000000 00000000
xhci_hcd : @19838290 00000000 00000000 00000000 00000000
xhci_hcd : @198382a0 00000000 00000000 00000000 00000000
xhci_hcd : @198382b0 00000000 00000000 00000000 00000000
xhci_hcd : @198382c0 00000000 00000000 00000000 00000000
xhci_hcd : @198382d0 00000000 00000000 00000000 00000000
xhci_hcd : @198382e0 00000000 00000000 00000000 00000000
xhci_hcd : @198382f0 00000000 00000000 00000000 00000000
xhci_hcd : @19838300 00000000 00000000 00000000 00000000
xhci_hcd : @19838310 00000000 00000000 00000000 00000000
xhci_hcd : @19838320 00000000 00000000 00000000 00000000
xhci_hcd : @19838330 00000000 00000000 00000000 00000000
xhci_hcd : @19838340 00000000 00000000 00000000 00000000
xhci_hcd : @19838350 00000000 00000000 00000000 00000000
xhci_hcd : @19838360 00000000 00000000 00000000 00000000
xhci_hcd : @19838370 00000000 00000000 00000000 00000000
xhci_hcd : @19838380 00000000 00000000 00000000 00000000
xhci_hcd : @19838390 00000000 00000000 00000000 00000000
xhci_hcd : @198383a0 00000000 00000000 00000000 00000000
xhci_hcd : @198383b0 00000000 00000000 00000000 00000000
xhci_hcd : @198383c0 00000000 00000000 00000000 00000000
xhci_hcd : @198383d0 00000000 00000000 00000000 00000000
xhci_hcd : @198383e0 00000000 00000000 00000000 00000000
xhci_hcd : @198383f0 19838000 00000000 00000000 00001802
xhci_hcd : Ring has not been updated
xhci_hcd : Ring deq = d9838000 (virt), 0x19838000 (dma)
xhci_hcd : Ring deq updated 0 times
xhci_hcd : Ring enq = d9838000 (virt), 0x19838000 (dma)
xhci_hcd : Ring enq updated 0 times
xhci_hcd : // xHC command ring deq ptr low bits + flags = @00000000
xhci_hcd : // xHC command ring deq ptr high bits = @00000000
xhci_hcd : ERST memory map follows:
xhci_hcd : @1ce92000 19838400 00000000 00000040 00000000
xhci_hcd : Event ring:
xhci_hcd : @19838400 00000000 00000000 00000000 00000000
xhci_hcd : @19838410 00000000 00000000 00000000 00000000
xhci_hcd : @19838420 00000000 00000000 00000000 00000000
xhci_hcd : @19838430 00000000 00000000 00000000 00000000
xhci_hcd : @19838440 00000000 00000000 00000000 00000000
xhci_hcd : @19838450 00000000 00000000 00000000 00000000
xhci_hcd : @19838460 00000000 00000000 00000000 00000000
xhci_hcd : @19838470 00000000 00000000 00000000 00000000
xhci_hcd : @19838480 00000000 00000000 00000000 00000000
xhci_hcd : @19838490 00000000 00000000 00000000 00000000
xhci_hcd : @198384a0 00000000 00000000 00000000 00000000
xhci_hcd : @198384b0 00000000 00000000 00000000 00000000
xhci_hcd : @198384c0 00000000 00000000 00000000 00000000
xhci_hcd : @198384d0 00000000 00000000 00000000 00000000
xhci_hcd : @198384e0 00000000 00000000 00000000 00000000
xhci_hcd : @198384f0 00000000 00000000 00000000 00000000
xhci_hcd : @19838500 00000000 00000000 00000000 00000000
xhci_hcd : @19838510 00000000 00000000 00000000 00000000
xhci_hcd : @19838520 00000000 00000000 00000000 00000000
xhci_hcd : @19838530 00000000 00000000 00000000 00000000
xhci_hcd : @19838540 00000000 00000000 00000000 00000000
xhci_hcd : @19838550 00000000 00000000 00000000 00000000
xhci_hcd : @19838560 00000000 00000000 00000000 00000000
xhci_hcd : @19838570 00000000 00000000 00000000 00000000
xhci_hcd : @19838580 00000000 00000000 00000000 00000000
xhci_hcd : @19838590 00000000 00000000 00000000 00000000
xhci_hcd : @198385a0 00000000 00000000 00000000 00000000
xhci_hcd : @198385b0 00000000 00000000 00000000 00000000
xhci_hcd : @198385c0 00000000 00000000 00000000 00000000
xhci_hcd : @198385d0 00000000 00000000 00000000 00000000
xhci_hcd : @198385e0 00000000 00000000 00000000 00000000
xhci_hcd : @198385f0 00000000 00000000 00000000 00000000
xhci_hcd : @19838600 00000000 00000000 00000000 00000000
xhci_hcd : @19838610 00000000 00000000 00000000 00000000
xhci_hcd : @19838620 00000000 00000000 00000000 00000000
xhci_hcd : @19838630 00000000 00000000 00000000 00000000
xhci_hcd : @19838640 00000000 00000000 00000000 00000000
xhci_hcd : @19838650 00000000 00000000 00000000 00000000
xhci_hcd : @19838660 00000000 00000000 00000000 00000000
xhci_hcd : @19838670 00000000 00000000 00000000 00000000
xhci_hcd : @19838680 00000000 00000000 00000000 00000000
xhci_hcd : @19838690 00000000 00000000 00000000 00000000
xhci_hcd : @198386a0 00000000 00000000 00000000 00000000
xhci_hcd : @198386b0 00000000 00000000 00000000 00000000
xhci_hcd : @198386c0 00000000 00000000 00000000 00000000
xhci_hcd : @198386d0 00000000 00000000 00000000 00000000
xhci_hcd : @198386e0 00000000 00000000 00000000 00000000
xhci_hcd : @198386f0 00000000 00000000 00000000 00000000
xhci_hcd : @19838700 00000000 00000000 00000000 00000000
xhci_hcd : @19838710 00000000 00000000 00000000 00000000
xhci_hcd : @19838720 00000000 00000000 00000000 00000000
xhci_hcd : @19838730 00000000 00000000 00000000 00000000
xhci_hcd : @19838740 00000000 00000000 00000000 00000000
xhci_hcd : @19838750 00000000 00000000 00000000 00000000
xhci_hcd : @19838760 00000000 00000000 00000000 00000000
xhci_hcd : @19838770 00000000 00000000 00000000 00000000
xhci_hcd : @19838780 00000000 00000000 00000000 00000000
xhci_hcd : @19838790 00000000 00000000 00000000 00000000
xhci_hcd : @198387a0 00000000 00000000 00000000 00000000
xhci_hcd : @198387b0 00000000 00000000 00000000 00000000
xhci_hcd : @198387c0 00000000 00000000 00000000 00000000
xhci_hcd : @198387d0 00000000 00000000 00000000 00000000
xhci_hcd : @198387e0 00000000 00000000 00000000 00000000
xhci_hcd : @198387f0 00000000 00000000 00000000 00000000
xhci_hcd : Ring has not been updated
xhci_hcd : Ring deq = d9838400 (virt), 0x19838400 (dma)
xhci_hcd : Ring deq updated 0 times
xhci_hcd : Ring enq = d9838400 (virt), 0x19838400 (dma)
xhci_hcd : Ring enq updated 0 times
xhci_hcd : ERST deq = 64'h19838400
xhci_hcd : // Set the interrupt modulation register
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 32'hf21fc624, 32'ha0, 4'hf);
xhci_hcd : // Enable interrupts, cmd = 0x4.
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 32'hf21fc020, 32'h4, 4'hf);
xhci_hcd : // Enabling event ring interrupter f21fc620 by writing 0x2 to irq_pending
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 32'hf21fc620, 32'h2, 4'hf);
xhci_hcd : f21fc620: ir_set[0]
xhci_hcd : f21fc620: ir_set.pending = 0x2
xhci_hcd : f21fc624: ir_set.control = 0xa0
xhci_hcd : f21fc628: ir_set.erst_size = 0x1
xhci_hcd : f21fc630: ir_set.erst_base = @1ce92000
xhci_hcd : f21fc638: ir_set.erst_dequeue = @19838400
xhci_hcd : Endpoint state = 0x1
xhci_hcd : Command ring enq = 0x19838010 (DMA)
xhci_hcd : // Turn on HC, cmd = 0x5.
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 32'hf21fc020, 32'h5, 4'hf);
xhci_hcd : // Ding dong!
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 32'hf21fc800, 32'h0, 4'hf);
xhci_hcd : Finished xhci_run
usb usb2: No SuperSpeed endpoint companion for config 1 interface 0 altsetting 0 ep 129: using minimum values
xhci_hcd : op reg status = 00000018
xhci_hcd : Event ring dequeue ptr:
xhci_hcd : @19838400 00000000 00000000 00000000 00000000
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 32'hf21fc024, 32'h18, 4'hf);
xhci_hcd : In xhci_handle_event
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 64'hf21fc638, 64'h19838408, 4'hf);
xhci_hcd : op reg status = 00000008
xhci_hcd : Event ring dequeue ptr:
xhci_hcd : @19838400 00000000 00000000 00000000 00000000
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 32'hf21fc024, 32'h8, 4'hf);
xhci_hcd : In xhci_handle_event
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 64'hf21fc638, 64'h19838408, 4'hf);
usb usb2: default language 0x0409
xhci_hcd : op reg status = 00000008
xhci_hcd : Event ring dequeue ptr:
xhci_hcd : @19838400 00000000 00000000 00000000 00000000
xhci_hcd : `MEM_WRITE_DWORD(3'b000, 32'hf21fc024, 32'h8, 4'hf);
...
It seems to be correct until "Finished xhci_run".
In "In xhci_handle_event" it does not handle the event correctly.
if ((event->event_cmd.flags & TRB_CYCLE) !=
xhci->event_ring->cycle_state) {
xhci->error_bitmask |= 1 << 2;
return;
}
The bit0 of event->event_cmd.flags is not set though the bit0 of xhci->event_ring->cycle_state is set. The handler returns with the error, and receives the same event again and again.
I cannot find the reason why event_cmd.flags is zero.
Thanks in advance,
Nishikawa
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