Praveena Nadahally wrote: > Does your solution supports mixing of DMA and PIO? The MUSB implementation in the OMAP2/3/4 processors does support mixing of DMA and PIO, as long as they are for different packets. For a given USB packet, mixing PIO and DMA accesses to the FIFO is not allowed. > The MUSB DMA doesn't support odd number of bytes or mixing 1/2/4 byte > access. That's not true for the Inventra engine in the OMAPs. They can handle odd-number of bytes. Accesses to the FIFOs will always be of the same size, except for leading and trailing parts of a packet and the DMA engine can adjust for that automatically. Does the DMA engine you use have the limitation you mentioned above? (Also, out of curiosity, do you have any public docs for your implementation? > So, we will need mixing of DMA and PIO mode for transfer. > There is a need to add the cache flush/invalidate code by default when > switching between PIO and DMA mode. The cache flush/invalidate code > needs to be added in the generic code as it already knows if a chain > is setup using DMA or not. Isn't it enough to do this in the MUSB code? I believe the current code can handle this okay - we're not breaking up a given transfer into part PIO and part DMA. We're saying the entire transfer will be by PIO if it is a control transfer and by DMA if it is not a control transfer. - Anand -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
