Re: [PATCH 10/25] ehci: Support Intel Moorestown EHCI controller SRAM QH/QTD/ITD/SITD pool caching

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> > diff --git a/drivers/usb/core/buffer.c b/drivers/usb/core/buffer.c
> > index 2c69654..150d4b8 100644
> > --- a/drivers/usb/core/buffer.c
> > +++ b/drivers/usb/core/buffer.c
> > @@ -115,6 +115,11 @@ void *hcd_buffer_alloc(
> >  		return kmalloc(size, mem_flags);
> >  	}
> >  
> > +	/* we won't use internal SRAM as data payload, we can't get
> > +	   any benefits from it */
> > +	if (hcd->has_sram && hcd->sram_no_payload)
> > +		return dma_alloc_coherent(NULL, size, dma,
> > mem_flags);
> 
> Why not pass the device you are allocing the memory from here?  You
> know what it is, right?

Yes - fixed.

> And this seems a bit odd, why is this the first controller that needs
> this type of allocation scheme?

Because existing controllers are either PIO or host DMA entirely. This
one has an SRAM cache of its own which has power and bus traffic
benefits.

Alan
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