Re: [PATCH 10/25] ehci: Support Intel Moorestown EHCI controller SRAM QH/QTD/ITD/SITD pool caching

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On Wed, Aug 04, 2010 at 10:50:50PM +0100, Alan Cox wrote:
> From: Jacob Pan <jacob.jun.pan@xxxxxxxxx>
> 
> The Intel Moorestown platform has MPH and OTG EHCI controllers that have
> internal SRAM that could be used as descriptors DMA pool caching. The SRAM is
> exposed via PCI BAR1. The limitation here is the SRAM access should be 32bit
> aligned. A separate patch "EHCI: Make ehci_qh structure items all 32bit aligned"
> has been submitted to linux-usb mailling list.
> 
> Signed-off-by: Jacob Pan <jacob.jun.pan@xxxxxxxxx>
> Signed-off-by: Alek Du <alek.du@xxxxxxxxx>
> Signed-off-by: Alan Cox <alan@xxxxxxxxxxxxxxx>
> ---
> 
>  drivers/usb/core/buffer.c   |   10 ++++++++++
>  drivers/usb/host/ehci-hcd.c |    3 ++-
>  drivers/usb/host/ehci-pci.c |   39 +++++++++++++++++++++++++++++++++++++++
>  drivers/usb/host/ehci.h     |    8 +++++++-
>  include/linux/usb/hcd.h     |    2 ++
>  5 files changed, 60 insertions(+), 2 deletions(-)
> 
> 
> diff --git a/drivers/usb/core/buffer.c b/drivers/usb/core/buffer.c
> index 2c69654..150d4b8 100644
> --- a/drivers/usb/core/buffer.c
> +++ b/drivers/usb/core/buffer.c
> @@ -115,6 +115,11 @@ void *hcd_buffer_alloc(
>  		return kmalloc(size, mem_flags);
>  	}
>  
> +	/* we won't use internal SRAM as data payload, we can't get
> +	   any benefits from it */
> +	if (hcd->has_sram && hcd->sram_no_payload)
> +		return dma_alloc_coherent(NULL, size, dma, mem_flags);

Why not pass the device you are allocing the memory from here?  You know
what it is, right?

> +
>  	for (i = 0; i < HCD_BUFFER_POOLS; i++) {
>  		if (size <= pool_max [i])
>  			return dma_pool_alloc(hcd->pool [i], mem_flags, dma);
> @@ -141,6 +146,11 @@ void hcd_buffer_free(
>  		return;
>  	}
>  
> +	if (hcd->has_sram && hcd->sram_no_payload) {
> +		dma_free_coherent(NULL, size, addr, dma);

Same here.

And this seems a bit odd, why is this the first controller that needs
this type of allocation scheme?

thanks,

greg k-h
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