On Fri, 2010-03-05 at 00:41 +0900, Paul Mundt wrote: > On Thu, Mar 04, 2010 at 03:29:38PM +0000, Catalin Marinas wrote: > > On Thu, 2010-03-04 at 14:21 +0000, James Bottomley wrote: > > > The thing which was discovered in this thread is basically that ARM is > > > handling deferred flushing (for D/I coherency) in a slightly different > > > way from everyone else ... > > > > Doing a grep for PG_dcache_dirty defined in terms of PG_arch_1 reveals > > that MIPS, Parisc, Score, SH and SPARC do similar things to ARM. PowerPC > > and IA-64 use PG_arch_1 as a clean rather than dirty bit. > > > SH used to use it as a PG_mapped which was roughly similar to the > PG_dcache_clean approach, at which point things like flushing for the PIO > case in the HCD wasn't necessary. It did result in rather aggressive over > flushing though, which is one of the reasons we elected to switch to > PG_dcache_dirty. > > Note that the PG_dcache_dirty semantics are also outlined in > Documentation/cachetlb.txt for PG_arch_1 usage, so it's hardly esoteric. Doing this way though is a lot more fragile... since page cache pages are no longer dirty by default, you need to ensure that any driver writing to one without DMA sets PG_arch_1, and as we've seen, this is generally not the case (it's almost never the case actually). Also, in the DMA case, you may not need to flush D$, but you -still- need to invalidate I$, and unless you then get another bit for tracking it, you end up doing a lot of over-invalidating of I$ no ? Or am I missing a critical piece of the puzzle ? Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
