On Thu, 2010-03-04 at 14:21 +0000, James Bottomley wrote: > The thing which was discovered in this thread is basically that ARM is > handling deferred flushing (for D/I coherency) in a slightly different > way from everyone else ... Doing a grep for PG_dcache_dirty defined in terms of PG_arch_1 reveals that MIPS, Parisc, Score, SH and SPARC do similar things to ARM. PowerPC and IA-64 use PG_arch_1 as a clean rather than dirty bit. -- Catalin -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
