On Thu, Mar 04, 2010 at 03:25:23PM +0000, Catalin Marinas wrote: > On Thu, 2010-03-04 at 14:27 +0000, Russell King - ARM Linux wrote: > > On Thu, Mar 04, 2010 at 07:51:52PM +0530, James Bottomley wrote: > > > On Thu, 2010-03-04 at 14:51 +0100, Pavel Machek wrote: > > > > Seems like ARM has requirement other architectures do not, that is > > > > a) not documented anywhere > > > > b) causes problems > > > > > > > > You could argue that performance improvement (how big is it, anyway?) > > > > is worth it, but this should be agreed to by wider community... > > > > > > Performance is always worth it provided we don't sacrifice correctness. > > > The thing which was discovered in this thread is basically that ARM is > > > handling deferred flushing (for D/I coherency) in a slightly different > > > way from everyone else ... once that's fixed, ARM will likely not have > > > the D/I problem, but we'll still have the libata (and other PIO systems) > > > D flushing issue. > > > > I think you've got that backwards. > > > > Reversing the meaning of PG_arch_1 will probably fix the D aliasing issue - > > since we'll interpret '0' to mean "page is dirty, it needs flushing before > > hitting userspace", whereas '1' means "page has been cleaned; there are no > > aliases." > > > > This doesn not address the I/D coherency issue, where the Icache needs > > attention to get rid of speculatively loaded cache lines while old data > > was present in the cache. > > The I-cache flushing is already handled in update_mmu_cache (or > set_pte_at in a future patch; I'm not talking about other issues on > ARM11MPCore here). You may not have been; my message was addressed to James to correct his message, which seems to have the issues confused. -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
