On Thu, 2010-03-04 at 15:41 +0000, Paul Mundt wrote: > On Thu, Mar 04, 2010 at 03:29:38PM +0000, Catalin Marinas wrote: > > On Thu, 2010-03-04 at 14:21 +0000, James Bottomley wrote: > > > The thing which was discovered in this thread is basically that ARM is > > > handling deferred flushing (for D/I coherency) in a slightly different > > > way from everyone else ... > > > > Doing a grep for PG_dcache_dirty defined in terms of PG_arch_1 reveals > > that MIPS, Parisc, Score, SH and SPARC do similar things to ARM. PowerPC > > and IA-64 use PG_arch_1 as a clean rather than dirty bit. > > SH used to use it as a PG_mapped which was roughly similar to the > PG_dcache_clean approach, at which point things like flushing for the PIO > case in the HCD wasn't necessary. It did result in rather aggressive over > flushing though, which is one of the reasons we elected to switch to > PG_dcache_dirty. Are you more in favour if a PIO kmap API than inverting the meaning of PG_arch_1? I'm not familiar with SH but for PIO devices the flushing shouldn't be more aggressive. For the DMA devices, Russell suggested that we mark the page as clean (set PG_dcache_clean) in the DMA API to avoid the default flushing. > Note that the PG_dcache_dirty semantics are also outlined in > Documentation/cachetlb.txt for PG_arch_1 usage, so it's hardly esoteric. Yes, but the flush_dcache_page() semantics outlined in the same file aren't followed by all the PIO drivers in the kernel. -- Catalin -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
