On Mon, Mar 01, 2010 at 10:39:14AM +0000, Catalin Marinas wrote: > On Sun, 2010-02-28 at 05:01 +0000, James Bottomley wrote: > > But the point of all of this is that I cache invalidation doesn't appear > > anywhere in the I/O path ... so if we're getting I/D incoherency, > > there's some problem in the mm code (or there's a missing arch > > assumption ... like I cache gets moved in more aggressively than we > > expect). Parisc is very sensitive to I/D incoherency, so we'd notice if > > there were a serious generic problem here. > > On ARM PIPT, it's probably because flush_cache_page isn't implemented. > But as I said above, given the speculative fetches I don't think it > would help much (well, it would work a bit better but not a complete > fix). Not quite. flush_cache_page() is called when we unmap or replace a page in userspace, which is completely the wrong place to do I-cache coherency when you have speculatively loaded caches - or even D-cache coherency if your cache behaves as a speculatively loaded PIPT or non-aliasing VIPT. Flushing the I-cache after a page has been in userspace does nothing to ensure that there aren't any I-cache lines associated with that page when you next come to map it into userspace. -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
