On Wed, Feb 17, 2010 at 08:05:43PM +1100, Benjamin Herrenschmidt wrote: > On Tue, 2010-02-16 at 09:22 +0100, Oliver Neukum wrote: > > This seems wrong to me. Buffers for control transfers may be > > transfered > > by DMA, so the caches must be flushed on architectures whose caches > > are not coherent with respect to DMA. > > > > Would you care to elaborate on the exact nature of the bug you are > > fixing? > > I missed part of this thread, so forgive me if I'm a bit off here, but > if the problem is indeed I$/D$ cache coherency vs. PIO transfers, then > this is a long solved issue on other archs such as ppc (and I _think_ > sparc). Nope. It's to do with mapping a buffer for DMA, and then doing PIO reads/writes to it. With speculative prefetches, you have to deal with cache coherency with hardware DMA on DMA unmap. If you've written to the buffer in violation of the DMA API buffer ownership rules, then your writes get thrown away resulting in immediate data corruption. -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
