On Tue, 2010-02-16 at 09:22 +0100, Oliver Neukum wrote: > This seems wrong to me. Buffers for control transfers may be > transfered > by DMA, so the caches must be flushed on architectures whose caches > are not coherent with respect to DMA. > > Would you care to elaborate on the exact nature of the bug you are > fixing? I missed part of this thread, so forgive me if I'm a bit off here, but if the problem is indeed I$/D$ cache coherency vs. PIO transfers, then this is a long solved issue on other archs such as ppc (and I _think_ sparc). The way we do it, at least on powerpc which is PIPT, is to keep track on a per-page basis, whether a given page is clean for execution using PG_arch1 bit. This bit is cleared when a new page is popped into the page cache, and we clear it from flush_dcache_page() iirc (you may want to dbl check I don't have the code at hand right now, or rather, I do but I'm to lazy to look right now :-) Any page with that not set is mapped into userspace with execute permission disabled. We do the flush and set PG_arch1 on the first exec fault to that page. Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
