On 07/11/2024 07:17, Krishna Kurapati wrote: > > > On 10/18/2024 11:57 AM, Krzysztof Kozlowski wrote: >> On Thu, Oct 17, 2024 at 05:10:54PM +0530, Uttkarsh Aggarwal wrote: >>> Adding a new 'snps,filter-se0-fsls-eop quirk' DT quirk to dwc3 core to set >>> GUCTL1 BIT 29. When set, controller will ignore single SE0 glitch on the >>> linestate during transmission. Only two or more SE0 is considered as >>> valid EOP on FS/LS port. This bit is applicable only in FS in device mode >>> and FS/LS mode of operation in host mode. >> >> Why this is not device/compatible specific? Just like all other quirks >> pushed last one year. > > Hi Krzysztof, > > Apologies for a late reply from our end. > > In DWC3 core/dwc3-qcom atleast, there have been no compatible specific > quirks added. Nothing stops from adding these, I think. > Also since this is a property of the Synopsys controller > hardware and not QC specific one, can we add it in bindings itself. > Because this is a property other vendors might also use and adding it > via compatible might not be appropriate. This does no answer my question. I don't see how this is not related to one specific piece of SoC. If you claim this is board-related, not SoC, give some arguments. Repeating the same is just no helping. Best regards, Krzysztof
