Hello,
Am Dienstag, 15. Oktober 2024, 13:10:17 CEST schrieb Xu Yang:
> Add usb3 phy and controller nodes for imx95.
>
> Signed-off-by: Xu Yang <xu.yang_2@xxxxxxx>
>
> ---
> Changes in v2:
> - no changes
> Changes in v3:
> - no changes
> Changes in v4:
> - reorder nodes
> Changes in v5:
> - no changes
> Changes in v6:
> - rebase to latest
> Changes in v7:
> - no changes
> Changes in v8:
> - no changes
> ---
> arch/arm64/boot/dts/freescale/imx95.dtsi | 43 ++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 03661e76550f..e3faa8462759 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1473,6 +1473,49 @@ smmu: iommu@490d0000 {
> };
> };
>
> + usb3: usb@4c010010 {
> + compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3";
> + reg = <0x0 0x4c010010 0x0 0x04>,
> + <0x0 0x4c1f0000 0x0 0x20>;
> + clocks = <&scmi_clk IMX95_CLK_HSIO>,
> + <&scmi_clk IMX95_CLK_32K>;
> + clock-names = "hsio", "suspend";
> + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
> + status = "disabled";
> +
> + usb3_dwc3: usb@4c100000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x4c100000 0x0 0x10000>;
> + clocks = <&scmi_clk IMX95_CLK_HSIO>,
> + <&scmi_clk IMX95_CLK_24M>,
> + <&scmi_clk IMX95_CLK_32K>;
> + clock-names = "bus_early", "ref", "suspend";
> + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&usb3_phy>, <&usb3_phy>;
> + phy-names = "usb2-phy", "usb3-phy";
> + snps,gfladj-refclk-lpm-sel-quirk;
> + snps,parkmode-disable-ss-quirk;
Downstream kernel also configures
> snps,tx-max-burst = /bits/ 8 <4>;
> snps,tx-thr-num-pkt = /bits/ 8 <1>;
is this not needed and omitted on purpose?
Best regards,
Alexander
> + iommus = <&smmu 0xe>;
> + };
> + };
> +
> + usb3_phy: phy@4c1f0040 {
> + compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy";
> + reg = <0x0 0x4c1f0040 0x0 0x40>,
> + <0x0 0x4c1fc000 0x0 0x100>;
> + clocks = <&scmi_clk IMX95_CLK_HSIO>;
> + clock-names = "phy";
> + #phy-cells = <0>;
> + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> + orientation-switch;
> + status = "disabled";
> + };
> +
> pcie0: pcie@4c300000 {
> compatible = "fsl,imx95-pcie";
> reg = <0 0x4c300000 0 0x10000>,
>
--
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