Currently the DWC3 driver supports only single port controller which requires at most two PHYs ie HS and SS PHYs. There are SoCs that has DWC3 controller with multiple ports that can operate in host mode. Some of the port supports both SS+HS and other port supports only HS mode. This change primarily refactors the Phy logic in core driver to allow multiport support with Generic Phy's. Changes have been tested on QCOM SoC SA8295P which has 4 ports (2 are HS+SS capable and 2 are HS only capable). Changes in v11: Implemented port_count calculation by reading interrupt-names from DT. Refactored IRQ handling in dwc3-qcom. Moving of macros to xhci-ext-caps.h made as a separate patch. Names of interrupts to be displayed on /proc/interrupts set to the ones present in DT. Changes in v10: Refactored phy init/exit/power-on/off functions in dwc3 core Refactored dwc3-qcom irq registration and handling Implemented wakeup for multiport irq's Moved few macros from xhci.h to xhci-ext-caps.h Fixed nits pointed out in v9 Fixed Co-developed by and SOB tags in patches 5 and 11 Changes in v9: Added IRQ support for DP/DM/SS MP Irq's of SC8280 Refactored code to read port count by accessing xhci registers Changes in v8: Reorganised code in patch-5 Fixed nitpicks in code according to comments received on v7 Fixed indentation in DT patches Added drive strength for pinctrl nodes in SA8295 DT Changes in v7: Added power event irq's for Multiport controller. Udpated commit text for patch-9 (adding DT changes for enabling first port of multiport controller on sa8540-ride). Fixed check-patch warnings for driver code. Fixed DT binding errors for changes in snps,dwc3.yaml Reabsed code on top of usb-next Changes in v6: Updated comments in code after. Updated variables names appropriately as per review comments. Updated commit text in patch-2 and added additional info as per review comments. The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected it in this version. Changes in v5: Added DT support for first port of Teritiary USB controller on SA8540-Ride Added support for reading port info from XHCI Extended Params registers. Changes in RFC v4: Added DT support for SA8295p. Changes in RFC v3: Incase any PHY init fails, then clear/exit the PHYs that are already initialized. Changes in RFC v2: Changed dwc3_count_phys to return the number of PHY Phandles in the node. This will be used now in dwc3_extract_num_phys to increment num_usb2_phy and num_usb3_phy. Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its structure such that the first half is for HS-PHY and second half is for SS-PHY. In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is present, pass proper SS_IDX else pass -1. Tests done on v11: a. ADB in device mode working on first port of SA8295P-ADP b. Enumeration on 4 ports of SA8295 tested by connecting pendrive, mouse and webcam / # lsusb -t Bus 002 Device 004: ID 046d:085e Bus 001 Device 001: ID 1d6b:0002 Bus 001 Device 008: ID 03f0:094a Bus 002 Device 003: ID 0781:558b Bus 002 Device 001: ID 1d6b:0003 Bus 001 Device 009: ID 046d:c05a / # dmesg | grep hub [ 1.168337] hub 1-0:1.0: USB hub found [ 1.168345] hub 1-0:1.0: 4 ports detected [ 1.169059] hub 2-0:1.0: USB hub found [ 1.169065] hub 2-0:1.0: 2 ports detected c. Wakeup tested on 4 ports of multiport by entering system suspend and connecting a device to each empty port and checking if it wakes up the system or not. This method was chosen because when we enter system suspend, power to connected peripherals was not present. So, the test was done by connecting a peripheral to empty port and seeing if the interrupts wake up the system or not. d. Enumeration and wakeup tested on single port controller of SC7280 in host mode. In this case, wakeup was initiated by a mouse click already connected to it. e. Interrupt registration tested on both single port and mulitport controllers of SA8295P-ADP. 184: 0 0 0 0 0 0 0 0 PDC 127 Level dp_hs_phy_1 185: 0 0 0 0 0 0 0 0 PDC 126 Level dm_hs_phy_1 186: 0 0 0 0 0 0 0 0 PDC 129 Level dp_hs_phy_2 187: 0 0 0 0 0 0 0 0 PDC 128 Level dm_hs_phy_2 188: 0 0 0 0 0 0 0 0 PDC 131 Level dp_hs_phy_3 189: 0 0 0 0 0 0 0 0 PDC 130 Level dm_hs_phy_3 190: 0 0 0 0 0 0 0 0 PDC 133 Level dp_hs_phy_4 191: 0 0 0 0 0 0 0 0 PDC 132 Level dm_hs_phy_4 192: 0 0 0 0 0 0 0 0 PDC 16 Level ss_phy_1 193: 0 0 0 0 0 0 0 0 PDC 17 Level ss_phy_2 194: 630 0 0 0 0 0 0 0 GICv3 165 Level xhci-hcd:usb1 195: 0 0 0 0 0 0 0 0 PDC 14 Level dp_hs_phy_irq 196: 0 0 0 0 0 0 0 0 PDC 15 Level dm_hs_phy_irq 197: 0 0 0 0 0 0 0 0 PDC 138 Level ss_phy_irq 198: 31 0 0 0 0 0 0 0 GICv3 835 Level dwc3 199: 0 0 0 0 0 0 0 0 PDC 12 Level dp_hs_phy_irq 200: 0 0 0 0 0 0 0 0 PDC 13 Level dm_hs_phy_irq 201: 0 0 0 0 0 0 0 0 PDC 136 Level ss_phy_irq Links to previous versions: Link to v10: https://lore.kernel.org/all/20230727223307.8096-1-quic_kriskura@xxxxxxxxxxx/ Link to v9: https://lore.kernel.org/all/20230621043628.21485-1-quic_kriskura@xxxxxxxxxxx/ Link to v8: https://lore.kernel.org/all/20230514054917.21318-1-quic_kriskura@xxxxxxxxxxx/ Link to v7: https://lore.kernel.org/all/20230501143445.3851-1-quic_kriskura@xxxxxxxxxxx/ Link to v6: https://lore.kernel.org/all/20230405125759.4201-1-quic_kriskura@xxxxxxxxxxx/ Link to v5: https://lore.kernel.org/all/20230310163420.7582-1-quic_kriskura@xxxxxxxxxxx/ Link to RFC v4: https://lore.kernel.org/all/20230115114146.12628-1-quic_kriskura@xxxxxxxxxxx/ Link to RFC v3: https://lore.kernel.org/all/1654709787-23686-1-git-send-email-quic_harshq@xxxxxxxxxxx/#r Link to RFC v2: https://lore.kernel.org/all/1653560029-6937-1-git-send-email-quic_harshq@xxxxxxxxxxx/#r Andrew Halaney (1): arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb controller Harsh Agarwal (1): usb: dwc3: core: Refactor PHY logic to support Multiport Controller Krishna Kurapati (11): dt-bindings: usb: qcom,dwc3: Add bindings for SC8280 Multiport dt-bindings: usb: Add bindings for multiport properties on DWC3 controller usb: xhci: Move extcaps related macros to respective header file usb: dwc3: core: Access XHCI address space temporarily to read port info usb: dwc3: core: Skip setting event buffers for host only controllers usb: dwc3: qcom: Add helper function to request threaded IRQ usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver usb: dwc3: qcom: Enable wakeup for applicable ports of multiport usb: dwc3: qcom: Add multiport suspend/resume support for wrapper arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280 arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB ports .../devicetree/bindings/usb/qcom,dwc3.yaml | 29 ++ .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 53 +++ arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 22 ++ arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 77 ++++ drivers/usb/dwc3/core.c | 324 +++++++++++++---- drivers/usb/dwc3/core.h | 16 +- drivers/usb/dwc3/drd.c | 15 +- drivers/usb/dwc3/dwc3-qcom.c | 328 ++++++++++++------ drivers/usb/host/xhci-ext-caps.h | 27 ++ drivers/usb/host/xhci.h | 27 -- 11 files changed, 708 insertions(+), 223 deletions(-) -- 2.40.0
