Add USB controller and USB PHY controller nodes for Exynos850 SoC.
The USB controller has next features:
- Dual Role Device (DRD) controller
- DWC3 compatible
- Supports USB 2.0 host and USB 2.0 device interfaces
- Supports full-speed (12 Mbps) and high-speed (480 Mbps) modes with
USB device 2.0 interface
- Supports on-chip USB PHY transceiver
- Supports up to 16 bi-directional endpoints (that includes control
endpoint 0)
- Complies with xHCI 1.00 specification
Only USB 2.0 is supported in Exynos850, so only UTMI+ PHY interface is
specified in "phys" property (index 0) and PIPE3 is omitted (index 1).
Signed-off-by: Sam Protsenko <semen.protsenko@xxxxxxxxxx>
---
arch/arm64/boot/dts/exynos/exynos850.dtsi | 30 +++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
index aa077008b3be..198d1dfcc672 100644
--- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -570,6 +570,36 @@ sysreg_cmgp: syscon@11c20000 {
clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>;
};
+ usbdrd: usb@13600000 {
+ compatible = "samsung,exynos850-dwusb3";
+ clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>,
+ <&cmu_hsi CLK_GOUT_USB_REF_CLK>;
+ clock-names = "bus_early", "ref";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x13600000 0x10000>;
+ status = "disabled";
+
+ usbdrd_dwc3: usb@0 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0x10000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usbdrd_phy 0>;
+ phy-names = "usb2-phy";
+ };
+ };
+
+ usbdrd_phy: phy@135d0000 {
+ compatible = "samsung,exynos850-usbdrd-phy";
+ reg = <0x135d0000 0x100>;
+ clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>,
+ <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>;
+ clock-names = "phy", "ref";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
usi_uart: usi@138200c0 {
compatible = "samsung,exynos850-usi";
reg = <0x138200c0 0x20>;
--
2.39.2
