On 8/11/2023 10:18 PM, Konrad Dybcio wrote:
On 21.07.2023 14:54, Johan Hovold wrote:
On Fri, Jul 21, 2023 at 02:10:07PM +0200, Konrad Dybcio wrote:
On 21.07.2023 13:16, Johan Hovold wrote:
On Fri, Jul 14, 2023 at 04:08:45PM +0530, Krishna Kurapati PSSNV wrote:
On 7/14/2023 2:30 PM, Johan Hovold wrote:
On Mon, Jul 03, 2023 at 12:35:48AM +0530, Krishna Kurapati PSSNV wrote:
On 6/27/2023 9:13 PM, Johan Hovold wrote:
On Wed, Jun 07, 2023 at 02:16:37PM +0200, Johan Hovold wrote:
On Sun, May 14, 2023 at 11:19:14AM +0530, Krishna Kurapati wrote:
- val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
- if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
- dev_err(qcom->dev, "HS-PHY not in L2\n");
+ for (i = 0; i < dwc->num_usb2_ports; i++) {
+ val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg_offset[i]);
+ if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
+ dev_err(qcom->dev, "HS-PHY%d not in L2\n", i);
+ }
When testing this on the X13s I get:
dwc3-qcom a4f8800.usb: HS-PHY2 not in L2
Sidenote, I get this on any Qcom device on any platform I try
to enter suspend on, without these MP patches.
Ok, that might provide some hint. But on sc8280xp (X13s) we only get it
on one of the four MP ports (i.e. on one out of six ports in total).
While on sa8295p-adp there are no such errors on any port.
I've been playing with 8450 and it looks like snps,dis_u2_susphy_quirk
causes this error.
The downstream tree contains this property and I'm inclined to believe
it means that this platforms should define it (as the devicetrees are
machine-generated to a degree, AFAIK), especially since this quirk does
the exact same thing on a known-working downstream, namely unsetting
DWC3_GUSB2PHYCFG_SUSPHY.
Digging a bit deeper, dwc3-msm-core [1], the downstream version of dwc3-qcom
performs a bit of a dance in a couple of places.. Look for that register name.
Unfortunately I have little idea what the "USB2 suspend phy" is.. is it a PHY
used in suspend? Is it the suspension of the USB2 PHY? No clue.
[1] https://git.codelinaro.org/clo/la/kernel/msm-5.10/-/blob/KERNEL.PLATFORM.1.0.r2-08800-WAIPIOLE.0/drivers/usb/dwc3/dwc3-msm-core.c
The description for that bit (BIT(6)) as per the databook is as follows:
---
6 SUSPENDUSB20 R_W Suspend USB2.0 HS/FS/LS PHY (SusPHY)
When set, USB2.0 PHY enters Suspend mode if Suspend
conditions are valid.
For DRD/OTG configurations, it is recommended that this bit is set
to 0 during coreConsultant configuration. If it is set to 1, then the
application must clear this bit after power-on reset. Application
needs to set it to 1 after the core initialization completes.
For all other configurations, this bit can be set to 1 during core
configuration.
Note:
■ In host mode, on reset, this bit is set to 1. Software can override
this bit after reset.
■ In device mode, before issuing any device endpoint command
when operating in 2.0 speeds, disable this bit and enable it after
the command completes. If you issue a command without
disabling this bit when the device is in L2 state and if mac2_clk
(utmi_clk/ulpi_clk) is gated off, the command will not get
completed
---
"L2" is the term we say when PHY is suspended, i.e., the main PLL is
shut off. Internally, I was able to find out that there are several
conditions where phy can fail to enter L2. The entry into L2 is
controlled by the USB controller itself, but can be limited by toggling
GUSB2PHY SUSPENDABLE bit. if that bit is 0 then controller won't place
HSPHY into L2. For the failure to enter L2, there can be several
situations, like there may be some pending line state change that
happened on the bus.
But Johan's error seems to be different as the register itself reads
zero which I don't understand.
Regards,
Krishna,
