From: Arnaud Mandy <ext-arnaud.2.mandy@xxxxxxxxx>
A new dma layer will be implemented on upcoming patches,
it was easier to remove the entire dma support on current
musb driver and restart from scratch.
Later patches will come implementing mode 1 support for
both Rx and Tx parts.
Signed-off-by: Arnaud Mandy <ext-arnaud.2.mandy@xxxxxxxxx>
[ removed plenty of dma code still sitting on that file ]
Signed-off-by: Felipe Balbi <felipe.balbi@xxxxxxxxx>
---
drivers/usb/musb/musb_gadget.c | 468 ++--------------------------------------
1 files changed, 15 insertions(+), 453 deletions(-)
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index 8b3c4e2..4e98a9a 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -117,24 +117,6 @@ __acquires(ep->musb->lock)
ep->busy = 1;
spin_unlock(&musb->lock);
- if (is_dma_capable()) {
- if (req->mapped) {
- dma_unmap_single(musb->controller,
- req->request.dma,
- req->request.length,
- req->tx
- ? DMA_TO_DEVICE
- : DMA_FROM_DEVICE);
- req->request.dma = DMA_ADDR_INVALID;
- req->mapped = 0;
- } else if (req->request.dma != DMA_ADDR_INVALID)
- dma_sync_single_for_cpu(musb->controller,
- req->request.dma,
- req->request.length,
- req->tx
- ? DMA_TO_DEVICE
- : DMA_FROM_DEVICE);
- }
if (request->status == 0)
DBG(5, "%s done request %p, %d/%d\n",
ep->end_point.name, request,
@@ -213,41 +195,6 @@ static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
return ep->packet_sz;
}
-
-#ifdef CONFIG_USB_INVENTRA_DMA
-
-/* Peripheral tx (IN) using Mentor DMA works as follows:
- Only mode 0 is used for transfers <= wPktSize,
- mode 1 is used for larger transfers,
-
- One of the following happens:
- - Host sends IN token which causes an endpoint interrupt
- -> TxAvail
- -> if DMA is currently busy, exit.
- -> if queue is non-empty, txstate().
-
- - Request is queued by the gadget driver.
- -> if queue was previously empty, txstate()
-
- txstate()
- -> start
- /\ -> setup DMA
- | (data is transferred to the FIFO, then sent out when
- | IN token(s) are recd from Host.
- | -> DMA interrupt on completion
- | calls TxAvail.
- | -> stop DMA, ~DMAENAB,
- | -> set TxPktRdy for last short pkt or zlp
- | -> Complete Request
- | -> Continue next request (call txstate)
- |___________________________________|
-
- * Non-Mentor DMA engines can of course work differently, such as by
- * upleveling from irq-per-packet to irq-per-buffer.
- */
-
-#endif
-
/*
* An endpoint is transmitting data. This can be called either from
* the IRQ routine or from ep.queue() to kickstart a request on an
@@ -262,7 +209,6 @@ static void txstate(struct musb *musb, struct musb_request *req)
void __iomem *epio = musb->endpoints[epnum].regs;
struct usb_request *request;
u16 fifo_count = 0, csr;
- int use_dma = 0;
musb_ep = req->ep;
@@ -295,113 +241,16 @@ static void txstate(struct musb *musb, struct musb_request *req)
epnum, musb_ep->packet_sz, fifo_count,
csr);
-#ifndef CONFIG_MUSB_PIO_ONLY
- if (is_dma_capable() && musb_ep->dma) {
- struct dma_controller *c = musb->dma_controller;
-
- use_dma = (request->dma != DMA_ADDR_INVALID);
-
- /* MUSB_TXCSR_P_ISO is still set correctly */
-
-#ifdef CONFIG_USB_INVENTRA_DMA
- {
- size_t request_size;
-
- /* setup DMA, then program endpoint CSR */
- request_size = min(request->length,
- musb_ep->dma->max_len);
- if (request_size < musb_ep->packet_sz)
- musb_ep->dma->desired_mode = 0;
- else
- musb_ep->dma->desired_mode = 1;
-
- use_dma = use_dma && c->channel_program(
- musb_ep->dma, musb_ep->packet_sz,
- musb_ep->dma->desired_mode,
- request->dma, request_size);
- if (use_dma) {
- if (musb_ep->dma->desired_mode == 0) {
- /*
- * We must not clear the DMAMODE bit
- * before the DMAENAB bit -- and the
- * latter doesn't always get cleared
- * before we get here...
- */
- csr &= ~(MUSB_TXCSR_AUTOSET
- | MUSB_TXCSR_DMAENAB);
- musb_writew(epio, MUSB_TXCSR, csr
- | MUSB_TXCSR_P_WZC_BITS);
- csr &= ~MUSB_TXCSR_DMAMODE;
- csr |= (MUSB_TXCSR_DMAENAB |
- MUSB_TXCSR_MODE);
- /* against programming guide */
- } else
- csr |= (MUSB_TXCSR_AUTOSET
- | MUSB_TXCSR_DMAENAB
- | MUSB_TXCSR_DMAMODE
- | MUSB_TXCSR_MODE);
-
- csr &= ~MUSB_TXCSR_P_UNDERRUN;
- musb_writew(epio, MUSB_TXCSR, csr);
- }
- }
-
-#elif defined(CONFIG_USB_TI_CPPI_DMA)
- /* program endpoint CSR first, then setup DMA */
- csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
- csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
- MUSB_TXCSR_MODE;
- musb_writew(epio, MUSB_TXCSR,
- (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
- | csr);
-
- /* ensure writebuffer is empty */
- csr = musb_readw(epio, MUSB_TXCSR);
-
- /* NOTE host side sets DMAENAB later than this; both are
- * OK since the transfer dma glue (between CPPI and Mentor
- * fifos) just tells CPPI it could start. Data only moves
- * to the USB TX fifo when both fifos are ready.
- */
-
- /* "mode" is irrelevant here; handle terminating ZLPs like
- * PIO does, since the hardware RNDIS mode seems unreliable
- * except for the last-packet-is-already-short case.
- */
- use_dma = use_dma && c->channel_program(
- musb_ep->dma, musb_ep->packet_sz,
- 0,
- request->dma,
- request->length);
- if (!use_dma) {
- c->channel_release(musb_ep->dma);
- musb_ep->dma = NULL;
- csr &= ~MUSB_TXCSR_DMAENAB;
- musb_writew(epio, MUSB_TXCSR, csr);
- /* invariant: prequest->buf is non-null */
- }
-#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
- use_dma = use_dma && c->channel_program(
- musb_ep->dma, musb_ep->packet_sz,
- request->zero,
- request->dma,
- request->length);
-#endif
- }
-#endif
-
- if (!use_dma) {
- musb_write_fifo(musb_ep->hw_ep, fifo_count,
- (u8 *) (request->buf + request->actual));
- request->actual += fifo_count;
- csr |= MUSB_TXCSR_TXPKTRDY;
- csr &= ~MUSB_TXCSR_P_UNDERRUN;
- musb_writew(epio, MUSB_TXCSR, csr);
- }
+ musb_write_fifo(musb_ep->hw_ep, fifo_count,
+ (u8 *) (request->buf + request->actual));
+ request->actual += fifo_count;
+ csr |= MUSB_TXCSR_TXPKTRDY;
+ csr &= ~MUSB_TXCSR_P_UNDERRUN;
+ musb_writew(epio, MUSB_TXCSR, csr);
/* host may already have the data when this message shows... */
DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
- musb_ep->end_point.name, use_dma ? "dma" : "pio",
+ musb_ep->end_point.name, "pio",
request->actual, request->length,
musb_readw(epio, MUSB_TXCSR),
fifo_count,
@@ -419,7 +268,6 @@ void musb_g_tx(struct musb *musb, u8 epnum)
u8 __iomem *mbase = musb->mregs;
struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
void __iomem *epio = musb->endpoints[epnum].regs;
- struct dma_channel *dma;
musb_ep_select(mbase, epnum);
request = next_request(musb_ep);
@@ -427,7 +275,6 @@ void musb_g_tx(struct musb *musb, u8 epnum)
csr = musb_readw(epio, MUSB_TXCSR);
DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
- dma = is_dma_capable() ? musb_ep->dma : NULL;
do {
/* REVISIT for high bandwidth, MUSB_TXCSR_P_INCOMPTX
* probably rates reporting as a host error
@@ -436,10 +283,6 @@ void musb_g_tx(struct musb *musb, u8 epnum)
csr |= MUSB_TXCSR_P_WZC_BITS;
csr &= ~MUSB_TXCSR_P_SENTSTALL;
musb_writew(epio, MUSB_TXCSR, csr);
- if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
- dma->status = MUSB_DMA_STATUS_CORE_ABORT;
- musb->dma_controller->channel_abort(dma);
- }
if (request)
musb_g_giveback(musb_ep, request, -EPIPE);
@@ -456,35 +299,8 @@ void musb_g_tx(struct musb *musb, u8 epnum)
DBG(20, "underrun on ep%d, req %p\n", epnum, request);
}
- if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
- /* SHOULD NOT HAPPEN ... has with cppi though, after
- * changing SENDSTALL (and other cases); harmless?
- */
- DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
- break;
- }
-
if (request) {
- u8 is_dma = 0;
-
- if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
- is_dma = 1;
- csr |= MUSB_TXCSR_P_WZC_BITS;
- csr &= ~(MUSB_TXCSR_DMAENAB
- | MUSB_TXCSR_P_UNDERRUN
- | MUSB_TXCSR_TXPKTRDY);
- musb_writew(epio, MUSB_TXCSR, csr);
- /* ensure writebuffer is empty */
- csr = musb_readw(epio, MUSB_TXCSR);
- request->actual += musb_ep->dma->actual_len;
- DBG(4, "TXCSR%d %04x, dma off, "
- "len %zu, req %p\n",
- epnum, csr,
- musb_ep->dma->actual_len,
- request);
- }
-
- if (is_dma || request->actual == request->length) {
+ if (request->actual == request->length) {
/* First, maybe a terminating short packet.
* Some DMA engines might handle this by
@@ -495,12 +311,6 @@ void musb_g_tx(struct musb *musb, u8 epnum)
&& (request->length
% musb_ep->packet_sz)
== 0)
-#ifdef CONFIG_USB_INVENTRA_DMA
- || (is_dma &&
- ((!dma->desired_mode) ||
- (request->actual &
- (musb_ep->packet_sz - 1))))
-#endif
) {
/* on dma completion, fifo may not
* be available yet ...
@@ -546,37 +356,6 @@ void musb_g_tx(struct musb *musb, u8 epnum)
/* ------------------------------------------------------------ */
-#ifdef CONFIG_USB_INVENTRA_DMA
-
-/* Peripheral rx (OUT) using Mentor DMA works as follows:
- - Only mode 0 is used.
-
- - Request is queued by the gadget class driver.
- -> if queue was previously empty, rxstate()
-
- - Host sends OUT token which causes an endpoint interrupt
- /\ -> RxReady
- | -> if request queued, call rxstate
- | /\ -> setup DMA
- | | -> DMA interrupt on completion
- | | -> RxReady
- | | -> stop DMA
- | | -> ack the read
- | | -> if data recd = max expected
- | | by the request, or host
- | | sent a short packet,
- | | complete the request,
- | | and start the next one.
- | |_____________________________________|
- | else just wait for the host
- | to send the next OUT token.
- |__________________________________________________|
-
- * Non-Mentor DMA engines can of course work differently.
- */
-
-#endif
-
/*
* Context: controller locked, IRQs blocked, endpoint selected
*/
@@ -592,106 +371,9 @@ static void rxstate(struct musb *musb, struct musb_request *req)
csr = musb_readw(epio, MUSB_RXCSR);
- if (is_cppi_enabled() && musb_ep->dma) {
- struct dma_controller *c = musb->dma_controller;
- struct dma_channel *channel = musb_ep->dma;
-
- /* NOTE: CPPI won't actually stop advancing the DMA
- * queue after short packet transfers, so this is almost
- * always going to run as IRQ-per-packet DMA so that
- * faults will be handled correctly.
- */
- if (c->channel_program(channel,
- musb_ep->packet_sz,
- !request->short_not_ok,
- request->dma + request->actual,
- request->length - request->actual)) {
-
- /* make sure that if an rxpkt arrived after the irq,
- * the cppi engine will be ready to take it as soon
- * as DMA is enabled
- */
- csr &= ~(MUSB_RXCSR_AUTOCLEAR
- | MUSB_RXCSR_DMAMODE);
- csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
- musb_writew(epio, MUSB_RXCSR, csr);
- return;
- }
- }
-
if (csr & MUSB_RXCSR_RXPKTRDY) {
len = musb_readw(epio, MUSB_RXCOUNT);
if (request->actual < request->length) {
-#ifdef CONFIG_USB_INVENTRA_DMA
- if (is_dma_capable() && musb_ep->dma) {
- struct dma_controller *c;
- struct dma_channel *channel;
- int use_dma = 0;
-
- c = musb->dma_controller;
- channel = musb_ep->dma;
-
- /* We use DMA Req mode 0 in rx_csr, and DMA controller operates in
- * mode 0 only. So we do not get endpoint interrupts due to DMA
- * completion. We only get interrupts from DMA controller.
- *
- * We could operate in DMA mode 1 if we knew the size of the tranfer
- * in advance. For mass storage class, request->length = what the host
- * sends, so that'd work. But for pretty much everything else,
- * request->length is routinely more than what the host sends. For
- * most these gadgets, end of is signified either by a short packet,
- * or filling the last byte of the buffer. (Sending extra data in
- * that last pckate should trigger an overflow fault.) But in mode 1,
- * we don't get DMA completion interrrupt for short packets.
- *
- * Theoretically, we could enable DMAReq irq (MUSB_RXCSR_DMAMODE = 1),
- * to get endpoint interrupt on every DMA req, but that didn't seem
- * to work reliably.
- *
- * REVISIT an updated g_file_storage can set req->short_not_ok, which
- * then becomes usable as a runtime "use mode 1" hint...
- */
-
- csr |= MUSB_RXCSR_DMAENAB;
-#ifdef USE_MODE1
- csr |= MUSB_RXCSR_AUTOCLEAR;
- /* csr |= MUSB_RXCSR_DMAMODE; */
-
- /* this special sequence (enabling and then
- * disabling MUSB_RXCSR_DMAMODE) is required
- * to get DMAReq to activate
- */
- musb_writew(epio, MUSB_RXCSR,
- csr | MUSB_RXCSR_DMAMODE);
-#endif
- musb_writew(epio, MUSB_RXCSR, csr);
-
- if (request->actual < request->length) {
- int transfer_size = 0;
-#ifdef USE_MODE1
- transfer_size = min(request->length,
- channel->max_len);
-#else
- transfer_size = len;
-#endif
- if (transfer_size <= musb_ep->packet_sz)
- musb_ep->dma->desired_mode = 0;
- else
- musb_ep->dma->desired_mode = 1;
-
- use_dma = c->channel_program(
- channel,
- musb_ep->packet_sz,
- channel->desired_mode,
- request->dma
- + request->actual,
- transfer_size);
- }
-
- if (use_dma)
- return;
- }
-#endif /* Mentor's DMA */
fifo_count = request->length - request->actual;
DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
@@ -701,23 +383,6 @@ static void rxstate(struct musb *musb, struct musb_request *req)
fifo_count = min_t(unsigned, len, fifo_count);
-#ifdef CONFIG_USB_TUSB_OMAP_DMA
- if (tusb_dma_omap() && musb_ep->dma) {
- struct dma_controller *c = musb->dma_controller;
- struct dma_channel *channel = musb_ep->dma;
- u32 dma_addr = request->dma + request->actual;
- int ret;
-
- ret = c->channel_program(channel,
- musb_ep->packet_sz,
- channel->desired_mode,
- dma_addr,
- fifo_count);
- if (ret)
- return;
- }
-#endif
-
musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
(request->buf + request->actual));
request->actual += fifo_count;
@@ -748,25 +413,17 @@ void musb_g_rx(struct musb *musb, u8 epnum)
void __iomem *mbase = musb->mregs;
struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
void __iomem *epio = musb->endpoints[epnum].regs;
- struct dma_channel *dma;
musb_ep_select(mbase, epnum);
request = next_request(musb_ep);
csr = musb_readw(epio, MUSB_RXCSR);
- dma = is_dma_capable() ? musb_ep->dma : NULL;
- DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
- csr, dma ? " (dma)" : "", request);
+ DBG(4, "<== %s, rxcsr %04x %p\n", musb_ep->end_point.name,
+ csr, request);
if (csr & MUSB_RXCSR_P_SENTSTALL) {
- if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
- dma->status = MUSB_DMA_STATUS_CORE_ABORT;
- (void) musb->dma_controller->channel_abort(dma);
- request->actual += musb_ep->dma->actual_len;
- }
-
csr |= MUSB_RXCSR_P_WZC_BITS;
csr &= ~MUSB_RXCSR_P_SENTSTALL;
musb_writew(epio, MUSB_RXCSR, csr);
@@ -790,58 +447,6 @@ void musb_g_rx(struct musb *musb, u8 epnum)
DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
}
- if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
- /* "should not happen"; likely RXPKTRDY pending for DMA */
- DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
- "%s busy, csr %04x\n",
- musb_ep->end_point.name, csr);
- goto done;
- }
-
- if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
- csr &= ~(MUSB_RXCSR_AUTOCLEAR
- | MUSB_RXCSR_DMAENAB
- | MUSB_RXCSR_DMAMODE);
- musb_writew(epio, MUSB_RXCSR,
- MUSB_RXCSR_P_WZC_BITS | csr);
-
- request->actual += musb_ep->dma->actual_len;
-
- DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
- epnum, csr,
- musb_readw(epio, MUSB_RXCSR),
- musb_ep->dma->actual_len, request);
-
-#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
- /* Autoclear doesn't clear RxPktRdy for short packets */
- if ((dma->desired_mode == 0)
- || (dma->actual_len
- & (musb_ep->packet_sz - 1))) {
- /* ack the read! */
- csr &= ~MUSB_RXCSR_RXPKTRDY;
- musb_writew(epio, MUSB_RXCSR, csr);
- }
-
- /* incomplete, and not short? wait for next IN packet */
- if ((request->actual < request->length)
- && (musb_ep->dma->actual_len
- == musb_ep->packet_sz))
- goto done;
-#endif
- musb_g_giveback(musb_ep, request, 0);
-
- request = next_request(musb_ep);
- if (!request)
- goto done;
-
- /* don't start more i/o till the stall clears */
- musb_ep_select(mbase, epnum);
- csr = musb_readw(epio, MUSB_RXCSR);
- if (csr & MUSB_RXCSR_P_SENDSTALL)
- goto done;
- }
-
-
/* analyze request if the ep is hot */
if (request)
rxstate(musb, to_musb_request(request));
@@ -968,22 +573,12 @@ static int musb_gadget_enable(struct usb_ep *ep,
musb_writew(regs, MUSB_RXCSR, csr);
}
- /* NOTE: all the I/O code _should_ work fine without DMA, in case
- * for some reason you run out of channels here.
- */
- if (is_dma_capable() && musb->dma_controller) {
- struct dma_controller *c = musb->dma_controller;
-
- musb_ep->dma = c->channel_alloc(c, hw_ep,
- (desc->bEndpointAddress & USB_DIR_IN));
- } else
- musb_ep->dma = NULL;
-
+ musb_ep->dma = NULL;
musb_ep->desc = desc;
musb_ep->busy = 0;
status = 0;
- pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
+ pr_debug("%s periph: enabled %s for %s %s, maxpacket %d\n",
musb_driver_name, musb_ep->end_point.name,
({ char *s; switch (musb_ep->type) {
case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
@@ -991,7 +586,6 @@ static int musb_gadget_enable(struct usb_ep *ep,
default: s = "iso"; break;
}; s; }),
musb_ep->is_in ? "IN" : "OUT",
- musb_ep->dma ? "dma, " : "",
musb_ep->packet_sz);
schedule_work(&musb->irq_work);
@@ -1133,28 +727,9 @@ static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
request->epnum = musb_ep->current_epnum;
request->tx = musb_ep->is_in;
- if (is_dma_capable() && musb_ep->dma) {
- if (request->request.dma == DMA_ADDR_INVALID) {
- request->request.dma = dma_map_single(
- musb->controller,
- request->request.buf,
- request->request.length,
- request->tx
- ? DMA_TO_DEVICE
- : DMA_FROM_DEVICE);
- request->mapped = 1;
- } else {
- dma_sync_single_for_device(musb->controller,
- request->request.dma,
- request->request.length,
- request->tx
- ? DMA_TO_DEVICE
- : DMA_FROM_DEVICE);
- request->mapped = 0;
- }
- } else if (!req->buf) {
+ if (!req->buf)
return -ENODATA;
- } else
+ else
request->mapped = 0;
spin_lock_irqsave(&musb->lock, lockflags);
@@ -1205,24 +780,11 @@ static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
/* if the hardware doesn't have the request, easy ... */
if (musb_ep->req_list.next != &request->list || musb_ep->busy)
musb_g_giveback(musb_ep, request, -ECONNRESET);
-
- /* ... else abort the dma transfer ... */
- else if (is_dma_capable() && musb_ep->dma) {
- struct dma_controller *c = musb->dma_controller;
-
- musb_ep_select(musb->mregs, musb_ep->current_epnum);
- if (c->channel_abort)
- status = c->channel_abort(musb_ep->dma);
- else
- status = -EBUSY;
- if (status == 0)
- musb_g_giveback(musb_ep, request, -ECONNRESET);
- } else {
+ else
/* NOTE: by sticking to easily tested hardware/driver states,
* we leave counting of in-flight packets imprecise.
*/
musb_g_giveback(musb_ep, request, -ECONNRESET);
- }
done:
spin_unlock_irqrestore(&musb->lock, flags);
--
1.6.4.2.253.g0b1fac
--
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