On Fri, 9 Oct 2009, Sarah Sharp wrote: > The EHCI specification says that an EHCI host controller may cache part of > the isochronous schedule. The EHCI controller must advertise how much it > caches in the schedule through the HCCPARAMS register isochronous > scheduling threshold (IST) bits. > > In theory, adding new iTDs within the IST should be harmless. The HW will > follow the old cached linked list and miss the new iTD. SW will notice HW > missed the iTD and return 0 for the transfer length. > > However, there have been reports of issues with a new Intel EHCI host > controller and full speed isoc endpoints. Can you describe which hardware this applies to? And does the bug affect high-speed isochronous endpoints? ... > @@ -1354,6 +1354,7 @@ iso_stream_schedule ( > period <<= 3; > > now = ehci_readl(ehci, &ehci->regs->frame_index) % mod; > + next = now + ehci->i_thresh; This should be next = (now + ehci->i_thresh) % mod; The rest is correct. Alan Stern -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
