> -----Original Message-----
> From: Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx>
> Sent: Saturday, May 28, 2022 9:06 AM
> To: Jun Li <jun.li@xxxxxxx>; gregkh@xxxxxxxxxxxxxxxxxxx; balbi@xxxxxxxxxx
> Cc: linux-usb@xxxxxxxxxxxxxxx; Thinh Nguyen <Thinh.Nguyen@xxxxxxxxxxxx>;
> J.D. Yue <jindong.yue@xxxxxxx>
> Subject: Re: [PATCH] usb: dwc3: add power down scale setting
>
> Li Jun wrote:
> > Some SoC(e.g NXP imx8MQ) may have a wrong default power down scale
> > setting so need init it to be the correct value, the power down
> > scale setting description in DWC3 databook:
> >
> > Power Down Scale (PwrDnScale)
> > The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock source to
> > a small part of the USB3 core that operates when the SS PHY is in its
> > lowest power (P3) state, and therefore does not provide a clock.
> > The Power Down Scale field specifies how many suspend_clk periods fit
> > into a 16 kHz clock period. When performing the division, round up the
> > remainder.
> > For example, when using an 8-bit/16-bit/32-bit PHY and 25-MHz Suspend
> > clock,
> > Power Down Scale = 25000 kHz/16 kHz = 13'd1563 (rounder up)
> >
> > So use the suspend clock rate to calculate it.
> >
> > Signed-off-by: Li Jun <jun.li@xxxxxxx>
> > ---
> > drivers/usb/dwc3/core.c | 22 ++++++++++++++++++++++
> > drivers/usb/dwc3/core.h | 1 +
> > 2 files changed, 23 insertions(+)
> >
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index e027c0420dc3..16d441dbc28b 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -1029,6 +1029,25 @@ static void dwc3_set_incr_burst_type(struct dwc3
> *dwc)
> > dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
> > }
> >
> > +static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
> > +{
> > + u32 reg, scale;
>
> Can we declare these variables in separate lines? Preferably reverse
> Christmas tree style.
Okay, will update in v2.
>
> > +
> > + if (!dwc->susp_clk)
> > + return;
> > +
> > + /*
> > + * The power down scale field specifies how many suspend_clk
> > + * periods fit into a 16KHz clock period. When performing
> > + * the division, round up the remainder.
> > + */
> > + scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16384);
>
> 16kHz == 16000Hz right?
yes, I misunderstood it, will update in v2.
Thanks
Li Jun
>
> > + reg = dwc3_readl(dwc->regs, DWC3_GCTL);
> > + reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
> > + reg |= DWC3_GCTL_PWRDNSCALE(scale);
> > + dwc3_writel(dwc->regs, DWC3_GCTL, reg);
> > +}
> > +
> > /**
> > * dwc3_core_init - Low-level initialization of DWC3 Core
> > * @dwc: Pointer to our controller context structure
> > @@ -1105,6 +1124,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
> > if (ret)
> > goto err1;
> >
> > + /* Set power down scale of suspend_clk */
> > + dwc3_set_power_down_clk_scale(dwc);
> > +
> > /* Adjust Frame Length */
> > dwc3_frame_length_adjustment(dwc);
> >
> > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > index 81c486b3941c..722808d8c0af 100644
> > --- a/drivers/usb/dwc3/core.h
> > +++ b/drivers/usb/dwc3/core.h
> > @@ -231,6 +231,7 @@
> >
> > /* Global Configuration Register */
> > #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
> > +#define DWC3_GCTL_PWRDNSCALE_MASK GENMASK(31, 19)
> > #define DWC3_GCTL_U2RSTECN BIT(16)
> > #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
> > #define DWC3_GCTL_CLK_BUS (0)
>
> Thanks,
> Thinh
