On Mon, May 02, 2022 at 02:36:34PM +0530, Rohit Agarwal wrote: > Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and > SNPS HS PHY on SDX65. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@xxxxxxxxxxx> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> Thanks, Mani > --- > arch/arm/boot/dts/qcom-sdx65.dtsi | 83 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 83 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index d989837..a64be20 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -126,6 +126,7 @@ > reg = <0x00100000 0x001f7400>; > clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; > clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; > + #power-domain-cells = <1>; > #clock-cells = <1>; > #reset-cells = <1>; > }; > @@ -139,6 +140,45 @@ > status = "disabled"; > }; > > + usb_hsphy: phy@ff4000 { > + compatible = "qcom,usb-snps-hs-7nm-phy"; > + reg = <0xff4000 0x120>; > + #phy-cells = <0>; > + status = "disabled"; > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + resets = <&gcc GCC_QUSB2PHY_BCR>; > + }; > + > + usb_qmpphy: phy@ff6000 { > + compatible = "qcom,sdx65-qmp-usb3-uni-phy"; > + reg = <0x00ff6000 0x1c8>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, > + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, > + <&gcc GCC_USB3_PRIM_CLKREF_EN>; > + clock-names = "aux", "cfg_ahb", "ref"; > + > + resets = <&gcc GCC_USB3PHY_PHY_BCR>, > + <&gcc GCC_USB3_PHY_BCR>; > + reset-names = "phy", "common"; > + > + usb_ssphy: phy@ff6200 { > + reg = <0x00ff6e00 0x160>, > + <0x00ff7000 0x1ec>, > + <0x00ff6200 0x1e00>; > + #phy-cells = <0>; > + #clock-cells = <0>; > + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; > + clock-names = "pipe0"; > + clock-output-names = "usb3_uni_phy_pipe_clk_src"; > + }; > + }; > + > system_noc: interconnect@1620000 { > compatible = "qcom,sdx65-system-noc"; > reg = <0x1620000 0x31200>; > @@ -178,6 +218,49 @@ > status = "disabled"; > }; > > + usb: usb@a6f8800 { > + compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; > + reg = <0x0a6f8800 0x400>; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, > + <&gcc GCC_USB30_MASTER_CLK>, > + <&gcc GCC_USB30_MSTR_AXI_CLK>, > + <&gcc GCC_USB30_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_SLEEP_CLK>; > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > + "sleep"; > + > + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 19 IRQ_TYPE_EDGE_BOTH>, > + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 18 IRQ_TYPE_EDGE_BOTH>; > + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", > + "ss_phy_irq", "dm_hs_phy_irq"; > + > + power-domains = <&gcc USB30_GDSC>; > + > + resets = <&gcc GCC_USB30_BCR>; > + > + usb_dwc3: usb@a600000 { > + compatible = "snps,dwc3"; > + reg = <0x0a600000 0xcd00>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0x1a0 0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_hsphy>, <&usb_ssphy>; > + phy-names = "usb2-phy", "usb3-phy"; > + }; > + }; > + > spmi_bus: qcom,spmi@c440000 { > compatible = "qcom,spmi-pmic-arb"; > reg = <0xc440000 0xd00>, > -- > 2.7.4 > -- மணிவண்ணன் சதாசிவம்